18
IBM
Eserver
p5 590 and 595 System Handbook
2.1 Server overview
The IBM
Sserver
p5 590 and 595 provides an expandable, high-end enterprise
solution for managing the computing requirements necessary to become an on
demand business. With the introduction of the POWER5 architecture, there has
been numerous improvements over the previous POWER4 architecture based
systems.
Both the p5-590 and p5-595 systems are based on the same 24-inch wide,
42 EIA height frame. Inside this frame all the server components are placed in
predetermined positions. This design and mechanical organization offers
advantages in optimization of floor space usage.
The p5-595 is a 16/32/48/64-way (at 1.9 GHz or 1.65 GHz) SMP system
packaged in a 24-inch wide 18 EIA by 36 inch deep CEC. The CEC is installed in
the 42 EIA base primary frame that also include two top mounted front and back
bulk power assemblies (BPAs) and support for up to four I/O drawers. A powered
I/O frame (FC 5792) and a bolt-on expansion frame (FC 8691) is also available to
support additional I/O drawers for the p5-595 system. Up to 12 I/O drawers can
be attached to a p5-595.
The p5-590 has identical architecture with p5-595. It differs from p5-595 in the
following areas:
Only a 1.65 GHz processor is supported in a p5-590.
The maximum configuration is a 32-way system with up to eight I/O drawers.
A powered I/O frame (FC 5792) is not required in the p5-590.
2.2 The POWER5 microprocessor
The POWER5 processor features single-threaded and multi-threaded execution,
providing higher performance in the single-threaded mode than its POWER4
predecessor provides at equivalent frequencies. The POWER5 microprocessor
maintains both binary and architectural compatibility with existing POWER4
systems to ensure that binaries continue executing properly and that all
application optimizations carry forward to newer systems. The POWER5
microprocessor provides additional enhancements such as virtualization,
simultaneous multi-threading support, improved reliability, availability, and
serviceability at both chip and system levels, and it has been designed to support
interconnection of 64 processors along with higher clock speeds.
Figure 2-1 shows the high-level structures of POWER4 and POWER5
processor-based systems. The POWER4 processors scale up to a 32-way
Содержание p5 590
Страница 2: ......
Страница 16: ...xiv IBM Eserver p5 590 and 595 System Handbook...
Страница 38: ...16 IBM Eserver p5 590 and 595 System Handbook...
Страница 106: ...84 IBM Eserver p5 590 and 595 System Handbook...
Страница 132: ...110 IBM Eserver p5 590 and 595 System Handbook...
Страница 160: ...138 IBM Eserver p5 590 and 595 System Handbook...
Страница 215: ...Chapter 7 Service processor 193 Figure 7 21 Current boot sequence menu default boot list...
Страница 216: ...194 IBM Eserver p5 590 and 595 System Handbook...
Страница 258: ...236 IBM Eserver p5 590 and 595 System Handbook Figure 8 34 Inventory Scout Figure 8 35 Select server to get VPD data...
Страница 264: ...242 IBM Eserver p5 590 and 595 System Handbook Figure 8 40 Detail view of a service event...
Страница 280: ...258 IBM Eserver p5 590 and 595 System Handbook...
Страница 285: ...Appendix C Installation planning 263 Figure C 1 Search for planning Figure C 2 Select 9119 590 and 9119 595...
Страница 286: ...264 IBM Eserver p5 590 and 595 System Handbook Figure C 3 Planning information...
Страница 298: ...276 IBM Eserver p5 590 and 595 System Handbook...
Страница 302: ...280 IBM Eserver p5 590 and 595 System Handbook...
Страница 312: ...290 IBM Eserver p5 590 and 595 System Handbook...
Страница 313: ...0 5 spine 0 475 0 875 250 459 pages IBM Eserver p5 590 and 595 System Handbook...
Страница 314: ......
Страница 315: ......