IBM p5 590, Системный справочник

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Chapter 2. Hardware architecture
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Single threaded operation
Not all applications benefit from simultaneous multi-threading. Having threads
executing on the same processor does not increase the performance of
processor intensive applications or applications that consume all of the chip’s
memory bandwidth. For this reason, the POWER5 processor supports the single
thread (ST) execution mode. In this mode, the POWER5 processor gives all of
the physical resources to the active thread, enabling it to achieve higher
performance than a POWER4 processor-based system at equivalent
frequencies. Highly optimized scientific codes are one example where ST
operation is ideal.
Simultaneous multi-threading and ST operation modes can be dynamically
switched without affecting server operations. The two modes can coexist on a
single physical system; however, only a single mode is possible on each OS
instance (partition).
2.2.2 Dynamic power management
In current CMOS
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technologies, chip power consumption is one of the most
important design parameters. With the introduction of simultaneous
multi-threading, more instructions execute per cycle per processor core, thus
increasing the core’s and the chip’s total switching power. To reduce switching
power, POWER5 chips extensively use a fine-grained, dynamic clock-gating
mechanism. This mechanism gates off clocks to a local clock buffer if dynamic
power management logic knows that the set of latches that are driven by the
buffer will not be used in the next cycle. This allows substantial power saving with
no performance impact. In every cycle, the dynamic power management logic
determines whether a local clock buffer that drives a set of latches can be
clock-gated in the next cycle.
In addition to the switching power, leakage power has become a performance
limiter. To reduce leakage power, the POWER5 chip uses transistors with low
threshold voltage only in critical paths. The POWER5 chip also has a low-power
mode, enabled when the system software instructs the hardware to execute both
threads at priority 1. In low power mode, instructions dispatch once every 32
cycles at most, further reducing switching power. Both threads are set to
priority 1 by the operating system when in the idle loop.
2.2.3 The POWER chip evolution
The p5-590 and p5-595 system complies with the RS/6000® platform
architecture, which is an evolution of the PowerPC Common Hardware
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Complementary Metal Oxide Semiconductor