170
IBM
Eserver
p5 590 and 595 System Handbook
7.1 Service processor functions
All IBM
Sserver
p5 590 and 595 servers are shipped with dual service
processor cards. One is considered the primary and the other secondary.
They are connected together over the Ethernet ports in the bulk power controller
(BPC).
It is IBMs intention to provide an automatic failover capability to the redundant
service processor in 2005. IBM plans to make the failover support available
through a no charge firmware upgrade 1H05.
The service processor is responsible for performing several functions within the
system. The purpose of this chapter is to accomplish the following:
Summarize how the service processor binary image is packaged and
executed on the platform.
Discuss how the service processor initiates the initial program load (IPL) for
the platform.
Introduce how to use the Advanced System Management Interface (ASMI) for
error reporting.
7.1.1 Firmware binary image
Each service processor has two updatable non-volatile dedicated flash memory
areas for storing the licensed internal code (LIC), also known as
firmware
. The
sides are named the temporary
t
and a permanent
p
side. The t-side is where
changes are generally applied and where the client generally runs from. The
p-side should be viewed as a well known backup level that the client can revert to
if necessary.
The CEC firmware binary image is a single image that includes code for the
service processor, the POWER Hypervisor, and platform partition firmware. This
CEC firmware binary image is stored on the system flash memory, as explained
in 2.5, “System flash memory configuration” on page 36. The firmware image for
the power code includes firmware for the bulk power controller, distributed
converter assembly (DCA), fans, and clustering switch. The power code binary
image is stored on the BPC service processor flash.
Note: All statements regarding IBM's plans, directions, and intent are subject
to change or withdrawal without notice, and represent goals and objectives
only.
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