HP 70340A, Руководство пользователя

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c.
T erminate the p o w er lev el en try b y selecting the
NNNNNNNNNNN
GHz softkey .
5.
Select
NNNNNNNNNNNNNNNNNNNNNNN
ALC INT to enable in ternal lev eling.
6.
If the RF output is curren tly turned o, select
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
AMPTD On Off to turn it on.
When the RF output is on, RF ON app ears in the display .
7. If necessary , turn o an y mo dulation: FM or LOG AM b y selecting the Mo dulation men u
and then pressing eac h function softkey so that O is underscored.
The display indicates whic h mo dulation t yp es are on or o.
8.
Select
NNNNNNNNNNNNNNNNNNNNNNN
Modultn ,
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
pulse modultn ,
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
gated pulse , and
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
GATED PULSE in order to turn on
gated pulse mo dulation.
When gated pulse mo dulation is turned on, the text \ Pulse Gated " app ears in the
display .
9. Set the desired pulse width.
F or example, p erform the follo wing pro cedure to set the pulse width to 100 s.
a.
Select
NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
PULSE WIDTH .
b.
T yp e 4 1 5 4 0 5 4 0 5 on the signal generator n umeric k eypad.
c.
T erminate the pulse width en try b y selecting the
NNNNNNNNNNN
MHz softkey .
10. Set the desired pulse repetition frequency , PRF.
F or example, p erform the follo wing pro cedure to set the pulse rep etition frequency to 1
kHz.
a. Select
NNNNNNNNNNN
PRF .
b.
T yp e 4 1 5 on the signal generator n umeric k eypad.
c.
T erminate the pulse rep etition frequency en try b y selecting the
NNNNNNNNNNN
KHz softkey .
When the gate signal from the gate signal source is at a TTL high lev el, RF pulses will
app ear at the signal generator RF OUTPUT connector for as long as the gate signal remains
high. If the gate signal switches to a TTL low lev el during when a pulse is presen t at the RF
OUTPUT , the last pulse will complete b efore the pulse train ceases. F or example, if the width
has b een set to 100 s and PRF has b een set to 1 kHz (PRI set to 1 ms), the pulses sho wn in
Figure 3-10 will result in a v alid gate signal.
3-22 Generating Signals
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