Honeywell
COMPONENT MAINTENANCE MANUAL
PART NUMBER 964-0452
I.B.1516A
Mar 30/01
23-12-01
output signal of 40MHz is brought to TTL level by transistors, V62 and V63, re-
spectively, and supplied to 4:1 divider, D16, or 5:1 divider, D17. The 10MHz out-
put frequency of the 4:1 divider is divided by 2 in D5-A, and then by 5. The 5MHz
signat is required as a clock pulse for digital direct synthesis (DDS) in loop 3.
The 1MHz output frequency from D5-A is supplied with the 1MHz signal from
the crystal oscillator to phase comparator, D15. If the frequency and phase of
the 2 input signals are the same, the output of the phase comparator is in the
tristate condition (high impedance).
If the signal produced by the VCO is advanced in phase; i.e, the VCO frequency
is too high, the output of the phase comparator assumes a LOW level for the
duration of the phase difference, and then returns to the tristate condition.
This brief LOW impulse results in a slight increase in output voltage at the output
of inverted integrator, N15-A. Consequently, the U-LOOP1 voltage, which is
supplied to tuning diode, V61, is reduced at the output of inverted amplifier,
N15-B, thus causing the frequency of the VCO to be decreased again. In this
way, the frequency of the VCO is synchronized with the accuracy of the crystaL
oscilLator at 40MHz.
The 40MHz signal, coupled out of the capacitive divider of the oscillator circuit,
is amplified in cascade amplifiers, V69, V70, V65, and drives the 2nd mixer. V60
is connected as an inverter and is used to reset the divider.
3
Loop 2
This loop generates an auxiliary frequency, which is a multiple of 100kHz be-
tween 41.8MHz and 69.8MHz. Ref. Fig. 10 for block diagram.
The VCO, with transistor, V20, is roughly preset and synchronized at the exact
frequency with tuning diode, V22. A data word is stored in Latch, D25, for the
presetting, depending upon the frequency set at the CDU according to Fig. 11.
The latch outputs assigned to data D9 to D12 connect to ground the 4 binary
scaled resistors, A13R11, A13R63, A13R57, and A13R23, via transistors,
A13V3, A13V1, A13V16, and A13V17.
Voltage, UST2, can therefore have 16 values, the lowest, about +6V, when all 4
data are high, and the highest, +12V, when all 4 data are LOW. It is present via
R78 at tuning diodes V17 and V18.
If a LOW is stored for data, D13, transistor, A13V18, is through-connected, and
a current of +5V flows on wire, VCO5, via R93 through switching diode, V14,
and coil, L3 to ground. As a result, C80 and trimmer, C81, are connected to the
oscillator circuit. If a HIGH was stored for data, D13, switching diode, V14, is dis-
abled via A13R28 with –9.1V. Similarly, a LOW for data, D14, results in capacitor
C95 and trimmer, C76, being connected to the oscillator circuit.
If a LOW is stored for data, D15, coil, L2, is connected parallel to coil, L3. To
prevent the amplitude of oscillations from falling as a result of this reduction in
the L/C ratio, resistor, A13Rl3, is by-passed with A13V6, and consequently, the
direct current in transistor, V20, is increased.
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