6. Series 8 I/O
Configuration
6.8. Defining Analog Output Channel Blocks
R500
Series 8 I/O User's Guide
187
April 2017
Honeywell
Maximum allowable lead
resistance - Note 1
(units are ohms)
Maximum allowable intrinsic
safety barrier resistance
(units are ohms)
RTD type
Entire loop
Per leg
Entire loop
Per leg
Pt:100 DIN characterization
20
10
18
18
Pt:100 JIS characterization
20
10
18
18
Ni: 120 Edison type 7
characterization
20
10
18
18
Cu: 10 SEER Standard
characterization
20
10
0
0
Cu50
20
10
0
0
Pt:1000
20
10
18
18
Note
:
Proper compensation for lead-wire resistance depends on the resistance being equal in each leg
of the RTD. This includes resistance due to lead-wire resistance and intrinsic safety barriers. No
provision is made to compensate for lead-wire resistance mismatch or intrinsic safety-barrier
resistance mismatch. Both the lead resistance and the intrinsic-safety-barrier resistance are
allowed simultaneously when connected to an RTD in a Division 1 area.
Checking and Filtering PV Range
PV range checking ensures that the PVCALC output of PV characterization is within the
limits defined by parameters PVEXEULO and PVEXEUHI. If either of the limits is
violated, the output of the PVAUTO is set to NaN if clamping has not been specified. If
clamping has been specified, the output of the PVAUTO is clamped to PVEXEUHI or
PVEXEULO, except when PVRAW, PVCALC, and PVAUTO are consequently set to
NaN.
If the range-checked and filtered value is less than the value specified by the user-
configured LOCUTOFF parameter, the final output called PVAUTO is forced to
PVEULO.
First order filtering is performed on PVCALC, as specified by the user through parameter
TF (filter lag time).