ROM CORRECTION
21-3
This chapter explains the functions and operations of ROM correction.
21.1 Overview of ROM Correction
When the setting of the address is the same as the ROM correction address registers, the INT9 instruction
will be executed. By processing the
INT9
interrupt service routine, the ROM correction function can be
achieved.
There are two address registers, in each containing a compare enable bit. When the address register and
the program counter match, and when the compare enable bit is at '1', then the CPU will be forced to
execute
INT9
instruction.
n
Block diagram of ROM correction
Figure 21.1
shows a block diagram of the ROM correction.
Fig. 21.1 Block Diagram of ROM Correction
n
ROM correction register
ROM correction address
register
Address latch
Detection bit
Reset
Comparitor
Set
F
2
MC-16LX
CPU core
F
2
MC-16LX bus
Enable bit
Bit No.
7
6
5
4
3
2
1
0
Initial value
PACSR Address: 00009E
H
Reserved
Reserved
Reserved
Reserved
AD1E
Reserved
AD0E
Reserved
----0-0-
B
—
—
—
—
R/W
—
R/W
—
PADR0 address: 1FF2
H
/1FF1
H
/1FF0
H
PADR1 address: 1FF5
H
/1FF4
H
/1FF3
H
byte
byte
byte
Access Initial value
R/W undefined
R/W undefined
Содержание MB90420/5 (A) Series
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