Fujitsu MB90420/5 (A) Series, Руководство по оборудованию

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TIMEPIECE TIMER
18-7
18.2.2 Sub-second Data Register
The sub-second data register stores reload values for the 21-bit prescaler that divides the oscillation clock.
The reload value is usually set so that the output cycle of the 21-bit prescaler becomes precisely 1 second.
n
Sub-second data register
[bits 20 to 0] D20 to D0
The sub-second data register stores reload values for the 21-bit prescaler. The reload value is reloaded
after the reload counter reaches 0. When changing all 3 bytes, be careful not to perform the reload
operation between write instructions. Otherwise, the 21-bit prescaler will load wrong data with a
combination of a new data byte and old data byte. Usually, the sub-second register should be rewritten
while the start bit is 0. When the sub-second register is set to 0, the 21-bit prescaler does not operate at
all.
The input clock frequency is designed to be always equal to 4 MHz of the oscillation clock. The reload
value for the 21-bit prescaler is typically 1E847F in hexadecimal, which is equal to “2
7
×
5
6
–1”. So, when
two such prescalers are combined, clock signals with a cycle of precisely 1 second are issued.
–– –– –– D20 D19 D18 D17 D16
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— — — (R/W) (R/W) (R/W) (R/W) (R/W)
— — — (X) (X) (X) (X) (X)
Sub-second data register
Address: 00395C
H
Read/write
Initial value
WTBRH
Bit No.
D15 D14 D13 D12 D11 D10 D9 D8
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
WTBRM
Bit No.
Sub-second data register
Address: 00395B
H
Read/write
Initial value
D7 D6 D5 D4 D3 D2 D1 D0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
WTBRL
Bit No.
Sub-second data register
Address: 00395A
H
Read/write
Initial value