Fujitsu MB90420/5 (A) Series, Руководство по оборудованию

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MB90420/5 (A) SERIES F
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
4-8
Table 4-1 Function of Each Bit of Clock Select Register (CKSCR)
Bit Name Function
bit 15 SCM: Machine
clock display bit
•
This bit to indicate whether the selected machine clock is the main clock or PLL clock.
•
When SCM is 0, it indicates that the sub-clock is selected; 1 indicates that the main
clock is selected.
•
When SCS = 1 and SCM = 1, it indicates that the main clock is during the oscillation
stabilization wait time for the main clock.
bit 14 MCM: Machine
clock display bit
•
This bit indicates whether the selected machine clock is the main clock or PLL clock.
•
When MCM is 0, it indicates the PLL clock is selected. When MCM is 1 it indicates
that the main clock is selected.
•
When MCS is 0 and MCM is 1, it indicates that the PLL clock is during the oscillation
stabilization wait time.
bit 13
bit 12 WS1, WS0:
Oscillation
stabilization wait
time select bits
•
These bits select oscillation stabilization wait time for oscillation clock at stop mode
cancellation, at transition from sub-clock mode to main clock mode, or at transition
from sub-clock mode to PLL clock mode
•
These bits are initialized to 11
B
at any reset factor.
Note: The oscillation stabilization wait time must be set to an appropriate value for the
oscillator. See
Section 3.2 . Set 00
B
only in the main clock mode.
[Reference]
When the PLL clock is used, the oscillation stabilization wait time is fixed to 2
14
/HCLK.
bit 11 SCS: Machine
clock select bit
(sub)
•
This bit specifies whether to select main clock or sub-clock as machine clock
•
When 1 is written with SCS 0, the oscillation stabilization wait period for the main clock
occurs, clearing the time-base timer automatically.
•
4-divided sub-clock is used for the operating clock at selecting the sub-clock. (The
machine clock is 8 kHz when the sub-oscillation is 32 kHz.)
•
When both SCS and MCS are 0, SCS is preferred and the sub-clock is selected.
•
This bit is initialized to 1 by all reset factors.
bit 10
MCS: Machine
clock select bit
•
This bit specifies where to select the main clock or PLL clock as the machine clock.
•
When MCS is 0 the PLL clock is selected with MCS 0, and the main clock is selected
with MCS1.
•
When 1 is written with MCS 0, the oscillation stabilization wait time for the PLL clock
occurs. Consequently, the time-base timer is cleared automatically, and the TBOF bit
of the time-base timer control register (TBTC) is also cleared.
•
The oscillation stabilization wait time for the PLL clock is always 2
14
/HCLK (When the
oscillation clock frequency is 4 MHz, the oscillation stabilization wait time is about 4.1
ms).
•
When the main clock is selected, the operating clock is the 2-divided oscillation clock
(operating clock is 2 MHz at 4 MHz oscillation clock frequency).
•
This bit is initialized to 1 at any reset factor.
Note: When 0 is written with MCS 1, make sure that the time-base timer interrupt is
masked using the TBIE bit of the time-base timer control register (TBTC) or
using the interrupt level register (ILM).
bit 9
bit 8 CS1, CS0:
Multiplication rate
select bits
•
These bits select the PLL clock multiplication rate.
•
One multiplication rate can be selected from four different rates.
•
They are initialized to 00
B
by all reset factor.
Note: When the MCS bit or MCM bit is 0, writing to these bits is inhibited. Set the
MCS bit to 1 (main clock mode), and then rewrite the CS1 bit and CS0 bit.
HCLK: Oscillation clock frequency