Fujitsu MB90420/5 (A) Series, Руководство по оборудованию

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PPG TIMER
13-9
n
PPG decrement counter register (PDCR)
This register can read the values of the 16-bit decrement counter.
Access this register using 16-bit data.
n
PPG cycle setting register (PCSR)
This is the cycle setting register with a buffer. Transfer from the buffer is performed by causing a counter
borrow.
At initializing or changing the cycle setting register, always to write to the duty setting register after writing to
the cycle setting register.
Access the cycle setting register using 16-bit data.
n
PPG duty setting register (PDUT)
This is the duty setting register with a buffer. Transfer from the buffer is performed by causing a counter
borrow.
When the value of the cycle setting register and the value of the duty setting register are the same, all Hs is
output when normal polarity is specified; all Ls is output when invert polarity is specified.
Do not set a value of “PCSR < PDUT”. Otherwise, the PPG output becomes undefined.
Access the duty setting register using 16-bit data.
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
(W) (W) (W) (W) (W) (W) (W) (W)
(X) (X) (X) (X) (x) (X) (X) (X)
PPG cycle setting register
(upper)
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(W) (W) (W) (W) (W) (W) (W) (W)
(X) (X) (X) (X) (x) (X) (X) (X)
Read/write
Initial value
PCSRH0 to 2
Address: ch0 003923
H
Address: ch1 00392B
H
Address: ch2 003933
H
Address: ch0 003922
H
Address: ch1 00392A
H
Address: ch2 003932
H
Read/write
Initial value
PCSRL0 to 2
PPG cycle setting register
(lower)
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
(R) (R) (R) (R) (R) (R) (R) (R)
(1) (1) (1) (1) (1) (1) (1) (1)
PPG decrement counter
register (upper)
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(R) (R) (R) (R) (R) (R) (R) (R)
(1) (1) (1) (1) (1) (1) (1) (1)
Read/write
Initial value
PDCRH0 to 2
Address: ch0 003921
H
Address: ch1 003929
H
Address: ch2 003931
H
Address: ch0 003920
H
Address: ch1 003928
H
Address: ch2 003930
H
Read/write
Initial value
PDCRL0 to 2
PPG decrement counter
register (lower)
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
(W) (W) (W) (W) (W) (W) (W) (W)
(X) (X) (X) (X) (x) (X) (X) (X)
PPG duty setting register
(upper)
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(W) (W) (W) (W) (W) (W) (W) (W)
(X) (X) (X) (X) (x) (X) (X) (X)
Read/write
Initial value
PDUTH0 to 2
Address: ch0 003925
H
Address: ch1 00392D
H
Address: ch2 003935
H
Address: ch0 003924
H
Address: ch1 00392C
H
Address: ch2 003934
H
Read/write
Initial value
PDUTL0 to 2
PPG duty setting register
(lower)