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I/O PORT

8-27

Block diagram of pins of port 5

Figure 8.5

shows the block diagram of the pins of port 5.

Fig. 8.5 Block Diagram of Pins of Port 5

Registers for port 5

The registers for port 5 are PDR5 and DDR5. The bits composing each register correspond to the pins of
port 5 1-to-1.

Table 8-20

shows the correspondence between the registers and the pins for port 5.

Table 8-20 Correspondence between Registers and Pins for Port 5

Port Name

Bits of Related Registers and Corresponding Pins

PDR5, DDR5

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Port 5

Corresponding pin

P57

P56

P55

P54

P53

P52

P51

P50

Internal data bus

PDR (port data register)

PDR read

PDR write

Output latch

DDR (port direction register)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

Resource output

Resource output enable

Resource input

Содержание MB90420/5 (A) Series

Страница 1: ...FUJITSU SEMICONDUCTOR MICROCONTROLLER MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL ...

Страница 2: ...ii ...

Страница 3: ...s not convey any license under the copy right patent right to trademarks claimed and owned by Fujitsu 4 Fujitsu reserved the right to change products or specifications without notice 5 No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Fujitsu 6 The products described in this document are not intend...

Страница 4: ...P SSP 2 19 2 7 3 Processor Status PS 2 21 2 7 4 Condition Code Register PS CCR 2 22 2 7 5 Register Bank Pointer PS RP 2 23 2 7 6 Interrupt Level Mask Register PS ILM 2 24 2 7 7 Program Counter PC 2 25 2 7 8 Direct Page Register DPR 2 26 2 7 9 Bank Register PCB DTB USB SSB and ADB 2 27 2 8 General purpose Register 2 28 2 9 Prefix Codes 2 30 2 9 1 Bank Select Prefix PCB DTB ADB and SPB 2 31 2 9 2 Co...

Страница 5: ...ns at Using Low power Consumption Mode 5 22 Chapter 6 Interrupt 6 1 6 1 Overview of Interrupt 6 3 6 2 Interrupt Factor and Interrupt Vector 6 5 6 3 Interrupt Control Registers and Resources 6 7 6 3 1 Interrupt Control Register ICR00 to ICR15 6 8 6 3 2 Function of Interrupt Control Register 6 10 6 4 Hardware Interrupt 6 13 6 4 1 Operation of Hardware Interrupt 6 15 6 4 2 Processing at Interrupt Ope...

Страница 6: ...tion of Port 5 8 29 8 8 Port 6 8 31 8 8 1 Registers for Port 6 PDR6 DDR6 8 33 8 8 2 Operation of Port 6 8 34 8 9 Port 7 8 36 8 9 1 Registers for Port 7 PDR7 DDR7 8 38 8 9 2 Operation of Port 7 8 39 8 10 Port 8 8 41 8 10 1 Registers for Port 8 PDR8 DDR8 8 43 8 10 2 Operation of Port 8 8 44 8 11 Port 9 8 46 8 11 1 Registers for Port 9 PDR9 DDR9 8 48 8 11 2 Operation of Port 9 8 49 8 12 Program Examp...

Страница 7: ...t Reload Timer 10 16 10 6 1 Internal Clock Mode Reload Mode 10 18 10 6 2 Internal Clock Mode One shot Mode 10 20 10 6 3 Event Count Mode 10 22 10 7 Precautions at Using 16 bit Reload Timer 10 24 10 8 Program Example of 16 bit Reload Timer 10 25 Chapter 11 Input Capture 11 1 11 1 Overview of Input Capture 11 3 11 2 Block Diagram of Input Capture 11 4 11 3 List of Input Capture Registers 11 5 11 3 1...

Страница 8: ...s for PPG Timer 13 5 13 3 1 List of PPG Timer Registers 13 5 13 3 2 Detailed Explanation of Registers for PPG Timer 13 6 13 4 Operation of PPG Timer 13 10 13 4 1 PWM Operation 13 10 13 4 2 One shot Operation 13 11 13 4 3 Interrupt Factors and Timing 13 12 Chapter 14 LCD Controller Driver 14 1 14 1 Overview of LCD Controller Driver 14 3 14 2 Configuration of LCD Controller Driver 14 4 14 2 1 Intern...

Страница 9: ...t Operation 16 12 16 5 1 External Interrupt Function 16 14 16 5 2 DTP Function 16 15 16 6 Precautions at Using DTP External Interrupt Circuit 16 16 16 7 Sample Programs for DTP External Interrupt Circuit 16 18 Chapter 17 Delayed Interrupt Generate Module 17 1 17 1 Overview of Delayed Interrupt Generate Module 17 3 17 2 Operation of Delayed Interrupt Generate Module 17 4 Chapter 18 Timepiece Timer ...

Страница 10: ...f ROM Correction 21 6 21 2 1 Correction Example of Program Errors 21 7 21 2 2 Example of Correction Processing 21 8 Chapter 22 ROM Mirror Function Select Module 22 1 22 1 Overview of ROM Mirror Function Select Module 22 3 22 2 ROM Mirror Function Select Register ROMM 22 4 Chapter 23 Can Controller 23 1 23 1 Features of CAN Controller 23 3 23 2 Block Diagram of CAN Controller 23 4 23 3 List of Over...

Страница 11: ...x 23 40 23 13 Setting Configuration of Multi level Message Buffer 23 41 23 14 CAN WAKE UP Function 23 43 Chapter 24 Low Voltage and CPU Operation Detection Reset Circuit 24 1 24 1 Overview of Low Voltage and CPU Operation Detection Reset Circuit 24 3 24 2 Configuration of Low Voltage and CPU Operation Detection Reset Circuit 24 4 24 3 Register for Low Voltage and CPU Operation Detection Reset Circ...

Страница 12: ...ns when Using Flash Memory 25 22 25 9 Sample Program for 1 Mbit Flash Memory 25 23 Chapter 26 Examples of MB90F428 A Serial Write Connection 26 1 26 1 Basic Configuration of MB90F428 A Serial Write Connection 26 3 26 2 Example of Serial Write Connection User Power Supply Used 26 5 26 3 Example of Serial Write Connection Power Supplied from the Writer 26 7 26 4 Example of Minimum Connection to the ...

Страница 13: ...Data Transfer to Accumulator 2 16 Fig 2 14 Example of Transfer between AL and AH of Accumulator A 8 bit immediate value zero extended 2 17 Fig 2 15 Example of Transfer between AL and AH of Accumulator A 8 bit immediate value sign extended 2 17 Fig 2 16 Example of 32 bit Data Transfer to Accumulator A register indirect 2 18 Fig 2 17 Example of Transfer between AL and AH of Accumulator A 16 bit regi...

Страница 14: ...er Consumption Mode Control Register LPMCR 5 7 Fig 5 4 Clock in CPU Intermittent Operation Mode 5 10 Fig 5 5 Cancellation of Sleep Mode by Interrupt 5 13 Fig 5 6 Cancellation of Timer Mode External Reset 5 16 Fig 5 7 Cancellation of Stop Mode External Reset 5 18 Fig 5 8 State Transition Diagram 5 19 Fig 6 1 General Flow of Interrupt Operation 6 4 Fig 6 2 Interrupt Control Register ICR00 to ICR15 a...

Страница 15: ...og Timer Interval Time 9 13 Fig 9 7 Operation of Time base Timer 9 18 Fig 10 1 Block Diagram of 16 bit Reload Timer 10 5 Fig 10 2 Block Diagram of Pins of 16 bit Reload Timer 10 7 Fig 10 3 Registers for 16 bit Reload Timer 10 8 Fig 10 4 Timer Control Status Register upper TMCSR0 1H 10 9 Fig 10 5 Timer Control Status Register lower TMCSR0 1L 10 11 Fig 10 6 16 bit Timer Register TMR0 1 10 13 Fig 10 ...

Страница 16: ...Fig 12 15 Transmit Data when Parity Enabled 12 30 Fig 12 16 Format of Transfer Data operation mode 2 12 31 Fig 12 17 Setting of Operation Mode 0 for UART1 12 33 Fig 12 18 Example of Bidirectional Communication Connection for UART1 12 33 Fig 12 19 Example of Bidirectional Communication Flow 12 34 Fig 12 20 Setting of Operation Mode 1 for UART1 12 35 Fig 12 21 Example of Master Slave Mode Communicat...

Страница 17: ...ter ELVR 16 10 Fig 16 7 DTP External Interrupt Circuit 16 12 Fig 16 8 Operation of DTP External Interrupt Circuit 16 13 Fig 16 9 Example of Interface with External Peripheral Unit 16 15 Fig 16 10 Clearing Factor Hold Circuit when Level Set 16 16 Fig 16 11 DTP External Interrupt Factor and Interrupt Request Issued when Interrupt Request Output Enabled 16 16 Fig 17 1 Block Diagram of Delayed Interru...

Страница 18: ... where Receive Messages Stored 23 35 Fig 23 7 Reception Flowchart for the CAN Controller 23 36 Fig 23 8 Example of Receive Interrupt Processing 23 40 Fig 23 9 Examples of Operation of Multi level Message Buffer 23 42 Fig 24 1 Block Diagram of Detection Reset Circuit for Low Voltage and CPU Operation 24 4 Fig 24 2 Low Voltage and CPU Operation Detection Reset Control Register LVRC 24 5 Fig 25 1 Blo...

Страница 19: ...eset Factor 3 11 Table 4 1 Function of Each Bit of Clock Select Register CKSCR 4 8 Table 5 1 Function of Each Bit of Low power Consumption Mode Control Register LPMCR 5 8 Table 5 2 Instructions At Transition To Low power Consumption Mode 5 9 Table 5 3 Operating State in Standby Mode 5 11 Table 5 4 Operation State in Low power Consumption Mode 5 20 Table 5 5 Each Pin State in Single Chip Mode 5 21 ...

Страница 20: ... Port 5 8 27 Table 8 21 Function of Registers for Port 5 8 28 Table 8 22 State of Port 5 Pins 8 30 Table 8 23 Pins of Port 6 8 31 Table 8 24 Correspondence between Registers and Pins for Port 6 8 32 Table 8 25 Function of Registers for Port 6 8 33 Table 8 26 State of Port 6 Pins 8 35 Table 8 27 Pins of Port 7 8 36 Table 8 28 Correspondence between Registers and Pins for Port 7 8 37 Table 8 29 Func...

Страница 21: ...2 Selection of Division Ratio to Obtain Synchronous Baud Rate 12 24 Table 12 13 Selection of Division Ratio to Obtain Asynchronous Baud Rate 12 25 Table 12 14 Baud Rate and Reload Value 12 26 Table 12 15 Operation Mode of UART 12 28 Table 12 16 Selection of Master Slave Mode Communication Function 12 36 Table 14 1 Combination of Bias and Duty 14 3 Table 14 2 LCD Driving Voltage Setting 14 8 Table ...

Страница 22: ...ection Reset Circuit for Low Voltage and CPU Operation 24 3 Table 24 2 Interval Time for CPU Operation Detection Reset Circuit 24 3 Table 24 3 Explanation of Function of Each Bit of Low Voltage and CPU Operation Detection Reset Control Register 24 6 Table 24 4 Operation Stabilization Wait Time 24 7 Table 25 1 Flash Memorr Control Signals 25 7 Table 25 2 Command Sequence List 25 10 Table 25 3 Bit A...

Страница 23: ... Overview of Product 1 3 1 2 Features 1 4 1 3 Block Diagram 1 6 1 4 Package Dimension 1 7 1 5 Pin Assignment 1 9 1 6 Pin Description 1 11 1 7 I O Circuits 1 14 1 8 Notes on Handling Devices 1 16 1 GENERAL ...

Страница 24: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 1 2 ...

Страница 25: ... On chip PLL clock multiplication system 1 2 3 4 and 1 2 for PLL stop time Minimum instruction execution time 62 5 ns 4 MHz 4 multiplied original oscillation ROM External FLASH ROM 128 KB MASK ROM 64 KB MASK ROM 128 KB RAM 6 KB 6 KB 4 KB 6 KB CAN Interface 2 ch 1 ch Low voltage detection reset Not provided Not provided Provided Not provided Provided Not provided Provided Package PGA 256 QFP100 Emu...

Страница 26: ...re 4 ch Detects rising edge falling edge or both edges 16 bit capture register 4 Latches counter value of 16 bit free run timer by detecting edge of pin input and issues interrupt request 16 bit PPG 3 ch Output pin 3 External trigger input pin 1 Operating clock frequency fcp fcp 2 2 fcp 2 4 and fcp 2 6 CAN Interface 1 Conforms to CAN Specifications Version 2 0 Part A and Part B Retransmits automat...

Страница 27: ... and program erase erase suspend erase restart commands Flag indicates completion of algorithm Flash writer by Minato Electronics Boot block configuration The erase command can be executed on a block by block basis Block protection by external programming voltage 1 The MB90420 A series has 2 ch and the MB90425 A series integrates 1 ch 2 This function is only provided for the MB90420A 5A series and...

Страница 28: ...ntroller External interrupt 8 ch P00 SIN0 INT4 P01 SOT0 INT5 P02 SCK0 INT6 P03 SIN1 INT7 P04 SOT1 P05 SCK1 TRG P06 PPG0 TOT1 P07 PPG1 TIN1 P57 SGA P56 SGO P55 RX0 P54 TX0 P53 INT3 P52 INT2 TX1 P51 INT1 RX1 P50 INT0 ADTG P91 P90 SEG23 SEG22 SEG11 SEG0 COM3 COM0 V3 V0 P47 P40 SEG21 SEG14 Note Specification of evaluation device MB90V420 No internal ROM is provided The size of the internal RAM is 6 KB...

Страница 29: ...20 5 A series n Package dimension FPT 100P M06 EIAJ code QFP100 P 1420 4 Lead pitch 0 65 mm Package width package length 14 20 mm Lead shape Gull wing Sealing type Plastic mold Length of flat portion 0 80 mm Plastic QFP 100 pins Plastic QFP 100 pins FPT 100P M06 Fig 1 2 Package Dimension QFP100 ...

Страница 30: ... MANUAL 1 8 n Package dimension FPT 100P M05 EIAJ code QFP100 P 1414 1 Lead pitch 0 50 mm Package width package length 14 14 mm Lead shape Gull wing Sealing type Plastic mold Plastic LQFP 100 pins Plastic LQFP 100 pins FPT 100P M05 Fig 1 3 Package Dimension LQFP100 Unit ...

Страница 31: ...P87 PWM2M3 P86 PWM2P3 P85 PWM1M3 P84 PWM1P3 DVCC P83 PWM2M2 P82 PWM2P2 P81 PWM1M2 P80 PWM1P2 DVSS P77 PWM2M1 P76 PWM2P1 P75 PWM1M1 P74 PWM1P1 DVCC P73 PWM2M0 P72 PWM2P0 P71 PWM1M0 P70 PWM1P0 DVSS P53 INT3 MD2 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36 SEG12 P37 SEG13 P40 SEG14 P41 SEG15 P42 SEG16 P43 SEG17 P44 SEG18 VCC P45 SEG19 P46 SEG20 P47 SEG21 C P90 SEG22...

Страница 32: ...WM2M0 P72 PWM2P0 P71 PWM1M0 P70 PWM1P0 DVSS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VSS SEG8 SEG9 SEG10 SEG11 P36 SEG12 P37 SEG13 P40 SEG14 P41 SEG15 P42 SEG16 P43 SEG17 P44 SEG18 VCC P45 SEG19 P46 SEG20 P47 SEG21 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6...

Страница 33: ...ose I O port SIN1 UART Ch 1 serial data input pin 86 88 INT7 G INT7 External interrupt input pin P04 General purpose I O port 87 89 SOT1 G UART Ch 1 serial data output pin P05 General purpose I O port SCK1 UART Ch 1 serial clock I O pin 88 90 TRG G 16 bit PPG ch 0 to 2 external trigger input pin P06 General purpose I O port PPG0 16 bit PPG ch 0 output pin 89 91 TOT1 G 16 bit reload timer ch1 TOT o...

Страница 34: ...to P67 General purpose I O port 36 to 39 41 to 44 38 to 41 43 to 46 AN0 to AN7 F A D Converter input pin P51 General purpose I O port INT1 INT1 External interrupt input pin 45 47 RX1 1 G CAN Interface 1 RX input pin P52 General purpose I O port INT2 INT2 External interrupt input pin 46 48 TX1 2 G CAN Interface 1 TX output pin P53 General purpose I O port 50 52 INT3 G INT3 External interrupt input ...

Страница 35: ...to 57 59 to 62 64 to 67 and 69 to 72 51 61 71 53 63 73 DVSS High current output buffer dedicated GND power pin pin number 54 to 57 59 to 62 64 to 67 and 69 to 72 32 34 AVCC A D Converter dedicated power input pin 35 37 AVSS A D Converter dedicated GND power pin 33 35 AVRH A D Converter Vref input pin Vref is fixed to AVSS 47 48 49 50 MD0 MD1 B Test mode input pin Connect these pins to VCC 49 51 MD...

Страница 36: ...1 4 I O Circuits Classification Circuit Remarks A X1 X0 Standby control signal Oscillation feedback resistor about 1 MΩ B Hysteresis input Has pull up resistor about 50 kΩ Hysteresis input C Hysteresis input Hysteresis input D Hysteresis input Has pull down resistor about 50 kΩ Hysteresis input Flash products do not have the pull down resistor Continue ...

Страница 37: ...LCDC Output CMOS Output LCDC Output Hysteresis input F Hysteresis input Analog input CMOS Output Hysteresis input Analog input G Hysteresis input CMOS Output Hysteresis input H Hysteresis input High current CMOS High current output Hysteresis input I LCDC Output LCDC Output ...

Страница 38: ...rating Also take care that the analog power AVCC AVRH DVCC and the analog input do not exceed the digital power VCC when turning the AC DC power on or off Stability of voltage supply A sudden change in the power supply voltage may cause a malfunction even within the operating assurance range of the VCC power supply voltage For safety the VCC ripple p p of the commercial frequency 50 to 60 MHz must...

Страница 39: ...r supply and ground outside the device to prevent decrease of unnecessary radiation the malfunction of the strobe signal due to a rise of ground level and follow the standards of total output current etc As shown in Figure 1 7 always set all VCC power pins to the same potential Also handle all VSS power pins in the same way as VCC power pins If there are plural VCC or VSS systems devices will not ...

Страница 40: ...or The MB90420 5 A series does not support internal pull up down resistors Use external components if necessary Output of undefined values from port at power on reset At a power on reset after power on undefined values are output from port 0 1 Note the following timing of undefined values Fig 1 8 Undefined value Output Timing Chart 1 At power on Original oscillation 217 period 8 192 ms when origin...

Страница 41: ...emory Space 2 4 2 3 Memory Map 2 6 2 4 Addressing 2 7 2 5 Allocation of Multi byte Length Data on Memory 2 11 2 6 Register 2 13 2 7 Dedicated Registers 2 14 2 8 General purpose Register 2 28 2 9 Prefix Codes 2 30 2 CPU ...

Страница 42: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 2 2 ...

Страница 43: ...bit processing The features of the F2 MC 16LX CPU are as follows n CPU Minimum instruction execution time 62 5 ns when operation performed at 4 MHz oscillation 4 multiplied Maximum memory space 16 Mbytes This is accessed in the linear bank type Instruction system optimized for controller Various data types Bit byte word and longword Extended addressing mode 23 types Enhanced high precision operati...

Страница 44: ...he memory map Fig 2 1 Example of Relationships between F2 MC 16LX System and Memory Map 1 The capacity of the internal ROM depends on the product 2 The area that can be accessed via the image depends on the product 3 The capacity of the internal RAM depends on the product 4 No access to this area in the single chip mode F2 MC 16LX Device Internal bus FFFFFFH FFFC00H FF0000H 1 100000H 010000H 00400...

Страница 45: ...llocated in this area This area is allocated to part of the RAM area and can also be used as ordinary RAM When this area is used as general purpose registers they can be accessed quickly using a short instruction through general purpose register addressing Expansion intelligent I O service EI 2 OS descriptor area address 000100H to 00017FH This area holds the transfer mode I O address transfer cou...

Страница 46: ...make efficient use of the small model of C compiler The lower 16 bit addresses of the FF bank are all designed to be the same so the table within ROM can be referred without declaring the far specification for the pointer For example when 00C000H is accessed actually the ROM data at FFC000H is accessed The ROM area of the FF bank exceeds 48 KB so the entire ROM area cannot be shown as an image at ...

Страница 47: ...accessed as continuous address space In bank addressing the 16 Mbyte memory space is divided into 256 managed banks of 64 Kbytes each Figure 2 3 shows an overview of the memory management in the linear and bank type Fig 2 3 Memory Management in Linear and Bank Types FFFFFFH 123456H 123456H Linear Types Bank Types 000000H 123456H 123456H FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H 64 kbyte FF b...

Страница 48: ...dress n Linear addressing by 24 bit operand specification Fig 2 4 Example of 24 bit Physical Direct Addressing in Linear Type n Addressing by 32 bit register indirect specification Fig 2 5 Example of 32 bit Ggeneral purpose Register Indirect Specification in Linear Type Old program counter program bank New program counter program bank JMPP 123456H 17 452D 12 3456 17452DH 123456H JMPP 123456H Next ...

Страница 49: ...Space for Each Bank Register and Major Use of Access Space Bank Register Name Access Space Major Use Initial Value At Reset Program bank register PCB Program PC space Stores instruction code vector tables immediate data etc FFH Data bank register DTB Data DT space Data that can be read written is stored and peripheral resource control registers and data registers are accessed 00H User stack bank r...

Страница 50: ...tary bank space corresponding to the prefix code accessible For details of the prefix codes see Section 2 9 Table 2 2 Addressing and Default Spaces Default Spaces Addressing Program space PC indirect addressing program access addressing branch instruction addressing Data space Addressing with RW0 RW1 RW4 and RW5 A addr16 dir Stack space Addressing with PUSHW POPW RW3 and RW7 Additional space Addre...

Страница 51: ... byte data in RAM Figure 2 7 shows the configuration of a multi byte length data in memory Lower 8 bits are allocated to n address and in order of n 1 n 2 and n 3 Fig 2 7 Storage of Multi byte Data in RAM n Storage of multi byte length operand Figure 2 8 shows the configuration of a multi byte length operand in memory Fig 2 8 Storage of Multi byte Operand MSB 01010101B LSB 01010101B 11001100B 1111...

Страница 52: ...nsequently for an instruction that accesses multi byte length data the address after the FFFFH address is the 0000H address of the same bank Figure 2 10 shows an example of access instruction for multi byte length data on the bank boundary Fig 2 10 Access to Multi byte Length Data on Bank Boundary RW1 6DH H Address n L F0H 35H A4H 35A4H RW1 35A4H RW3 6DF0H State of stack after execution of PUSHW i...

Страница 53: ... register is the same as the dedicated registers in that it can be accessed without address specification but like ordinary memory it can be specified by the user Figure 2 11 shows the allocation of the dedicated and the general purpose registers Fig 2 11 Dedicated and General purpose Registers CPU Dedicated register Accumulator User stack pointer System stack pointer Processor status Program coun...

Страница 54: ...It can also be used as one 32 bit register AH AL User stack pointer USP This is a 16 bit pointer that indicates the user stack address System stack pointer SSP This is a 16 bit pointer that indicates the system stack address Processor status PS This is a 16 bit register that indicates the system status Program counter PC This is a 16 bit register that indicates the current instruction store locati...

Страница 55: ... x x Program counter PC Value in reset vector data at FFFFDCH and FFFFDDH Direct page register DPR 01H Program bank register PCB Value in reset vector data at FFFFDEH Data bank register DTB 00H User stack bank register USB 00H System stack bank register SSB 00H Additional data bank register ADB 00H Not used x Undefined Note The above initial values are the device initial values not for the ICE suc...

Страница 56: ...rocess 32 bit data long word 16 bit data word and 8 bit data byte There are also 4 bit transfer instructions MOVN but they are explained here as 8 bit data When processing 32 bit data the AH register and the AL register are concatenated and used When processing 16 or 8 bit data only the AL register is used When transferring data equal to or shorter than the byte length to the AL register the data ...

Страница 57: ...f Transfer between AL and AH of Accumulator A 8 bit immediate value sign extended Before execution MOV A 3000H B53000H X Undefined MSB Most Significant Bit LSB Least Significant Bit DTB Data bank register This instruction zero extends the data at address 3000H and stores the extended data in the AL register After execution XXXXH 2456H 2456H 0088H B5H DTB 77H 88H MSB LSB Memory space AH AL Before e...

Страница 58: ...g using the result obtained by adding the 8 bit length offset to data of RW1 and then stores the read value in the A register After execution XXXXH XXXXH 8F74H 2B52H A6H DTB 8FH 74H MSB LSB Memory space 15H 38H 2BH 52H 6 AH AL Before execution MOVW A RW1 6 A61540H A6153EH RW1 X Undefined MSB Most Significant Bit LSB Least Significant Bit DTB Data bank register This instruction performs word length...

Страница 59: ...two types of stacks can be used system stack and user stack The stack address is determined by the S flag of the processor status PS CCR as shown in Table 2 4 Table 2 4 Stack Address Specification Stack Address S flag Upper 8 bits Lower 16 bits 0 User stack bank register USB User stack pointer USP 1 System stack bank register SSB System stack pointer SSP Initial value The S flag is initialized to ...

Страница 60: ...k operation are indicated by the system stack bank register SSB n User stack pointer USP When using the user stack pointer USP set the S flag of the condition code register CCR in the processor status PS to 0 In this case the upper 8 bits of the address used for the stack operation are indicated by the user stack bank register USB Before execution PUSHW A when S flag 0 C6F326H X Undefined MSB Most...

Страница 61: ...ing The value of this register is compared to the value of the interrupt level setting bits of the interrupt control register ICR IL0 to IL2 corresponding to the interrupt request of each peripheral resource Register bank pointer RP This pointer specifies the starting address of the memory block register bank used as the general purpose register in the RAM area General purpose registers have 32 ba...

Страница 62: ...a reset Sticky bit flag T This flag is set to 1 when data shifted out by a carry contains at least one 1 at execution of the logical shift to right instruction or the arithmetical shift to right instruction Otherwise this flag is set to 0 This flag is also set to 0 when the shift amount is zero Negative flag N This flag is set to 1 when the MSB of the operation result is 1 This flag is cleared to ...

Страница 63: ...between the RP data and the real addresses are shown as the conversion rules in Figure 2 22 Fig 2 22 Physical Address Conversion Rules in General purpose Register Area RP has value ranging from 00H to 1FH Consequently the starting address of the register bank can be set in the range of 000180H to 00037FH The assembler instruction can use the 8 bit immediate value transfer instruction that is trans...

Страница 64: ...upt request of a smaller value than the value of these bits is issued When the interrupt is accepted its interrupt level value is set in the interrupt level mask register ILM and subsequent interrupts of a level equal to or lower than that level are no longer accepted All bits of the interrupt level mask register ILM are initialized to 0 by a reset Consequently the interrupt level of this register...

Страница 65: ...of that address are specified for PC The address actually used is the 24 bit address of which the 8 bits and 16 bits are compounded Figure 2 24 The PC data is updated by executing the conditional branch instruction the subroutine call instruction by an interrupt or reset etc The PC can also be used as the base pointer when reading the operand Fig 2 24 Program Counter PC Note Neither the PC nor the...

Страница 66: ...to 01H by a reset Also the DPR can be read and written by an instruction Fig 2 25 Generation of Physical Addressing in Direct Page Register DPR Figure 2 26 shows the direct page register DPR setting and an example of data access Fig 2 26 Direct Page Register DPR Setting and Data Access Example DTB register AAAAAAAA DPR register BBBBBBBB Direct address during instruction CCCCCCCC 24 bit physical ad...

Страница 67: ...e entire 16 Mbyte space at executing a software interrupt instruction or at a hardware interrupt or exception Data bank register DTB The DTB specifies the data DT space User stack bank register USB and system stack bank register SSB The USB and SSB indicate the stack SP space Whether the USB or the SSB is used depends on the value of the S flag in the processor status PS CCR For details see Sectio...

Страница 68: ... bank pointer RP is used to specify the bank to be used When the RP is read the currently used bank is indicated The RP determines the starting address of each bank as the following expression Starting address of general purpose register 000180H RP 10H Figure 2 27 shows the allocation and configuration of the general purpose register banks in memory space Fig 2 27 Allocation and Configuration of G...

Страница 69: ... meaning that the state before the reset is held However at power on the value is undefined Table 2 6 shows the typical function of the general purpose register Table 2 6 Typical Function of the General Purpose Register Register Name Function R0 to R7 Used as operands for various instructions Note R0 can also be used as the barrel shift instruction counter or the normalize normalization instructio...

Страница 70: ...ix the memory space accessed by the instruction can be selected arbitrarily irrespective of the addressing type Common register bank prefix CMR When an instruction that accesses the register bank is prefixed by a common register bank prefix all the access destination of the instruction can be changed to the common bank at 000180H to 00018FH the common bank is the register bank selected when RP 0 i...

Страница 71: ...ck space is used When the bank select prefix is used some instructions perform an exceptional operation Table 2 8 shows the instructions not affected by the bank select prefix and Table 2 9 shows the instructions requiring care when using the bank select prefix Table 2 8 Instructions Unaffected by Bank Select Prefix Instruction Type Instruction Results String instructiondd MOVS MOVSW SCEQ SCWEQ FI...

Страница 72: ...me defined register bank relatively easily irrespective of the value of the current register bank pointer RP For this end the F 2 MC 16LX has register bank called the common bank that can be shared between each task The common bank is at addresses 000180H to 00018FH When an instruction that accesses the register bank is prefixed by the common register bank prefix CMR all the access destination of ...

Страница 73: ...OVSW SCEQ SCWEQ FILS FILSW Do not add the NCC prefix to the string instructions Flag change instruction AND CCR imm8 OR CCR imm8 The condition code register CCR changes according to the instruction specification irrespective of the prefix The prefix affects up to the next instruction PS return instruction POPW PS The condition code register CCR changes according to the instruction specification ir...

Страница 74: ...nd Interrupt hold Inhibit Instruction Prefix Code Interrupt Hold Inhibit Instruction instruction that delays effect of prefix code Instruction that does not accept interrupt request or hold request PCB DTB ADB SPB CMR NCC MOV LM imm8 OR CCR imm8 AND CCR imm8 POPW PS Interrupt hold inhibition As shown in Figure 2 28 the interrupt request or the hold request is not accepted during execution of the p...

Страница 75: ...nhibit instruction Fig 2 29 Interrupt hold Inhibition Instruction and Prefix Code n Successive prefix codes As shown in Figure 2 30 when some conflicting prefix codes PCB ADB DTB SPB are successive the last one is effective Fig 2 30 Successive Prefix Codes Interrupt hold inhibit instruction CCR is not changed by the NCC MOV A FFH NCC MOV ILM imm8 CCR XXX10XXB CCR XXX10XXB ADD A 01H Prefix codes Pr...

Страница 76: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 2 36 ...

Страница 77: ... Overview of Reset 3 3 3 2 Reset Factors and Oscillation Stabilization Wait Time 3 5 3 3 External Reset Pin 3 7 3 4 Reset Operation 3 8 3 5 Reset Factor Bit 3 10 3 6 State of Each Pin at Reset 3 12 3 RESET ...

Страница 78: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 3 2 ...

Страница 79: ...d None Detection of low voltage When low power supply voltage detected Main clock MCLK Stopped Awaited CPU operation detection function When overflow occurs in CPU operation detection function counter Main clock MCLK Stopped None MCLK Main clock 2 divided oscillation clock This factor causes a reset only for the MB90420A Series and MB90425A series External reset An external reset is generated when...

Страница 80: ...s lower than the predetermined value The oscillation stabilization wait time is fixed to 218 oscillation clock cycles 218 HCLK A reset is performed after the oscillation stabilization wait time has elapsed This function works only for the MB90420A MB90425A series with the low voltage detection reset circuit and always starts at power on CPU Operation detection reset The CPU operation detection res...

Страница 81: ... Watchdog Overflow of watchdog timer Not taken However the WS1 and WS0 bits are initialized to 11 External Input L level to RSTX pin Not taken However the WS1 and WS0 bits are initialized to 11 Low voltage detection Detection of low power supply voltage 218 HCLK about 65 536 ms CPU Operation detection Overflow of CPU operation detection timer Not taken However the WS1 and WS0 bits are initialized ...

Страница 82: ...quency Note The oscillator of ceramic or crystal requires an oscillation stabilization wait time from the start of oscillation until the stable oscillation generally ranging from a few ms to dozens of ms Set the value appropriate for the oscillator being used For details see Section 4 1 n Oscillation stabilization wait reset state The power on reset stop mode or reset in the sub clock mode is perf...

Страница 83: ...y by a reset during write the input to the RSTX pin is accepted in a cycle that does not damage memory Initialization of the internal circuit requires the clocks In particular when an external clock is used for initialization the clock must be input at the reset input Block diagram of external reset pin Fig 3 2 Block Diagram of External Reset Pin Pin RSTX Pch Nch Synchronization circuit HCLK Oscil...

Страница 84: ...ata are fetched in the reset sequence For details of the mode pins see Section 7 1 n Mode fetch When the reset is cancelled the reset vector and mode data are transferred by hardware to the relevant register within the CPU core The reset vector and mode data are allocated to FFFFDCH to FFFFDFH 4 bytes At reset cancellation the CPU outputs these addresses to the bus and fetches the reset vector and...

Страница 85: ...etting becomes valid after the reset For details of the mode deta see Section 7 1 Reset vector address FFFFDCH to FFFFDEH The execution starting address is written after termination of the reset Execution starts at this address FFFFDFH FFFFDEH FFFFDDH FFFFDCH Memory space Mode data Reset vector bits 23 to 16 Reset vector bits 15 to 8 Reset vector bits 7 to 0 F2 MC 16LX CPU Core Mode register Micro...

Страница 86: ... branch to the appropriate program Fig 3 7 Block Diagram of Reset Factor Bit S Set R Reset O Output F F Flip Flop Watchdog timer control register WDTC Power on Power on reset detector External reset request detector RSTX Pin Watchdog timer reset detector Detector for writing to RST bit of LPMCR Delay circuit No periodic clear RST bit set Clear Internal data bus RSTX L S R F F O S R F F O S R F F O...

Страница 87: ...C is also set to 1 n Notes on reset factor bit At plural reset factor When plural reset factors occur the corresponding reset factor bits of the watchdog timer control register WDTC are set to 1 For example when an external reset request from the RSTX pin and a watchdog timer overflow occur simultaneously the ERST and WRST bits are set to 1 Power on reset At power on reset the PONR bit is set to 1...

Страница 88: ...gh impedance state and the mode data read destination is the internal ROM n State of pins after mode data read The state of the pins after the mode data is read is determined by the mode data M1 and M0 00 When single chip mode selected M1 and M0 00B The I O pins resource pins are all set to the high impedance state and the mode data read destination is the internal ROM Note Make sure that pins set...

Страница 89: ...lock 4 3 4 2 Block Diagram of Clock Generation Section 4 5 4 3 Clock Select Register CKSCR 4 7 4 4 Clock Mode 4 9 4 5 Oscillation Stabilization Wait Time 4 12 4 6 Connection of Oscillator and External Clock 4 13 4 CLOCK ...

Страница 90: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 4 2 ...

Страница 91: ... clock Sub clock SCLK The sub clock is either generated by attaching the oscillator to the X0A X1A pin or by dividing the externally input clock by 4 The sub clock is the low speed machine clock that is used when the watch timer is in input clock sub clock mode Main clock MCLK The main clock is 2 devided oscillation clock and is the clock input to the time base timer and clock selector PLL Clock P...

Страница 92: ...n Pin X0A X1A Clock generation circuit Pin Pin X0 X1 2 devided clock 4 devided clock Clock selector 1 2 3 4 SCLK Sub clock PCLK PLL clock φ Machine clock MCLK Main clock HCLK Oscillation clock CPU Pin Pin PPG0 to PPG2 RX0 1 Resources 16 bit PPG timer 0 1 2 CAN controller 0 1 Pin TRG Pin TX0 1 Pin SGA SG0 Pin V0 to V3 Pin COM0 to COM3 SEG0 to SEG23 Pin SCK0 SCK1 Pin SIN0 SIN1 Pin SOT0 SOT1 Pin TIN0...

Страница 93: ...ster LPMCR CPU operating clock Resource function operating clock CPU Intermittent operation cycle selector STP SLP SPL RST RESV CG1 CG0 RESV Resource clock control circuit CPU Clock control circuit Time base timer Oscillation stabilization wait time selector To watchdog timer Clock select register CKSCR 4 divided clock S Q R SCM MCM WS1 WS0 SCS MCS CS0 CS1 2 Stop signal Machine clock S Q R S Q R R...

Страница 94: ... PLL oscillation and is supplied to the CPU clock selector Clock selector The clock to be supplied to the CPU clock control and resource clock circuit is selected from the main clock and four different PLL clocks Clock select register CKSCR This register switches between the oscillation clock and the PLL clock selects the oscillation stabilization wait time and the PLL clock multiplication rate Os...

Страница 95: ...plication Rate Select Bits The parenthesized values are the values when the oscillation clock is 4 MHz 0 0 1 HCLK 4 MHz 0 1 2 HCLK 8 MHz 1 0 3 HCLK 12 MHz 1 1 4 HCLK 16 MHz MCS Machine Clock Select Bit 0 The PLL clock is selected 1 The main clock is selected SCS Machine Clock Select Bit Sub 0 The sub clock is selected 1 The main clock is selected WS1 WS0 Oscillation Stabilization Wait Time Select ...

Страница 96: ... oscillation stabilization wait period for the main clock occurs clearing the time base timer automatically 4 divided sub clock is used for the operating clock at selecting the sub clock The machine clock is 8 kHz when the sub oscillation is 32 kHz When both SCS and MCS are 0 SCS is preferred and the sub clock is selected This bit is initialized to 1 by all reset factors bit 10 MCS Machine clock s...

Страница 97: ...LL clock Transition from PLL clock mode to main clock mode When the MCS bit of the CKSCR is rewritten from 0 to 1 in the PLL clock mode the PLL clock switches to the main clock when the edge of the PLL clock matches the edge of the main clock after 1 to 8 PLL clocks Transition from main clock mode to sub clock mode When the SCS bit of the CKSCR is rewritten from 1 to 0 in the main clock mode the m...

Страница 98: ... the machine clock make sure that the machine clock is switched by referencing the MCM bit or SCS bit of the CKSCR When the SCS bit and the MCS bit are both 0 the SCS bit is preferred causing the sub clock mode n Selection of PLL clock multiplication rate When one of 00B to 11B is written to the CS1 bit and CS0 bit of the CKSCR one PLL clock multiplication rate can be selected from the four differ...

Страница 99: ...tion waiting termination CS1 CS0 10 5 PLL Clock oscillation stabilization waiting termination CS1 CS0 11 6 1 write to MCS bit The hardware standby and the watchdog reset included 7 Synchronous timing of PLL clock and main clock 8 0 write to SCS bit 9 Synchronous timing of main clock and sub clock 10 1 write to SCS bit 11 Main clock oscillation stabilization waiting termination 12 Main clock oscill...

Страница 100: ... after oscillation starts and then the clock is supplied to the CPU when the oscillation stabilization wait time has elapsed and oscillation is well stabilized The time required for oscillation to stabilize depends on the type of the oscillator crystal ceramic etc so the appropriate oscillation stabilization wait time must be selected for the oscillator type The oscillation stabilization wait time...

Страница 101: ...nnection of oscillator and external clock Connection example for crystal or ceramic oscillator Connect a crystal or ceramic oscillator as shown in Figure 4 6 Fig 4 6 Connection of Crystal or Ceramic Oscillator Connection of external clock Connect the external clock to X0 X0A pin and leave X1 X1A pin open as shown in Figure 4 7 Fig 4 7 Connection of External Clock X0 X0A MB90420 5 A X1 X1A X0 X0A M...

Страница 102: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 4 14 ...

Страница 103: ...roller 5 5 5 3 Low power Consumption Mode Control Register LPMCR 5 7 5 4 CPU Intermittent Operation Mode 5 10 5 5 Standby Mode 5 11 5 6 State Transition Diagram 5 19 5 7 Pin State in Standby Mode at Reset 5 21 5 8 Precautions at Using Low power Consumption Mode 5 22 5 LOW POWER CONSUMPTION MODE ...

Страница 104: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 5 2 ...

Страница 105: ...e relationships between the CPU operation mode and current consumption Fig 5 1 CPU Operating Mode and Current Consumption Current consumption PLL Clock mode PLL Clock intermittent operation mode CPU Operation mode Standby mode Sleep mode 10n mA Time base timer mode Stop mode 4 multiplied clock 3 multiplied clock 2 multiplied clock 1 multiplied clock 4 multiplied clock 3 multiplied clock 2 multipli...

Страница 106: ...sumption controller is used to stop supply of the clock to the CPU sleep mode to the CPU and resources time base timer mode or to stop the oscillation clock stop mode to reduce the power consumption PLL Sleep mode In PLL sleep mode the CPU operating clock stops in the PLL clock mode Everything except the CPU operates on the PLL clock Main sleep mode In main sleep mode the CPU operating clock stops...

Страница 107: ...R SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register CKSCR Pin Hi Z control Resource clock controller Stop sleep signal Cancellation of interrupt Oscillation stabilization wait time selector CPU Intermittent operation selector 2048 divided clock 4 divided clock 4 divided clock 8 divided clock Main clock Time base timer Pin high impedance controller Standby controller Internal reset generator pi...

Страница 108: ...o the CPU This circuit controls the clock supplied to clock controller for resource Resource clock controller Controls the clock supplied to the resource Pin high impedance controller Sets the external pin to the high impedance state in the time base timer mode or the stop mode Isolates the pull up resistor in the stop mode for a pin for which the pull up option is selected Internal reset generato...

Страница 109: ...ays write 1 to this bit CG1 CG0 CPU Suspended Clock Count Select Bit 0 0 0 clock CPU clock resource clock 0 1 8 clocks CPU clock resource clock 1 about 3 to 4 1 0 16 clocks CPU clock resource clock 1 about 5 to 6 1 1 32 clocks CPU clock resource clock 1 about 9 to 10 TMD Time base Timer Mode Bit 0 Transition to time base timer mode 1 Writing 1 to this bit does not affect operation RST Internal Res...

Страница 110: ...ition to the time base timer mode or stop mode is performed 0 is always read from this bit bit 5 SPL Pin state specification bit In timer time base timer or stop mode This bit is only valid in the time base timer mode or stop mode When this bit is 0 the level of the external pin is held When this bit is 1 the external pin is set to high impedance This bit is initialized to 0 at a reset bit 4 RST I...

Страница 111: ...iting to the low power consumption mode control register in word length make sure to write at an even number address Transition to the low power consumption mode by writing at an odd number address may cause malfunction n Priority of STP SLP and TMD bits When the stop mode request sleep mode request and time base timer mode request are issued simultaneously the priority is as follows stop mode req...

Страница 112: ... consumption The CG1 and CG0 bits of the low power consumption mode control register LPMCR CG1 CG0 are used to select the suspended clock count to be supplied to the CPU The same clock as the one supplied to the resource is used at external bus operation The instruction execution time when the CPU intermittent operation mode is used can be calculated by adding the compensation value which the inst...

Страница 113: ...me base timer mode SPL 0 SCS 1 TMD 0 Held Time base timer mode Time base timer mode SPL 1 SCS 1 TMD 0 Operate Stop 1 Hi z Timer mode SPL 0 SCS 0 TMD 0 Held Timer mode Timer mode SPL 1 SCS 0 TMD 0 Operate Stop 2 Hi z Stop mode SPL 0 STP 1 Held Stop mode Stop mode SPL 1 STP 1 Stop Stop Stop Stop Stop Hi z Reset Interrupt 1 The time base timer and the clock timer operate 2 The watch timer operates SP...

Страница 114: ...rmed to the main sleep mode when the MCS 1 SCS 1 and a transition is performed to the sub sleep mode when the SCS 0 Note When 1 is written simultaneously to the SLP and the STP bits the STP is preferred transiting to the stop mode When 1 is written to the SLP and 0 is written to the TMD simultaneously the TMD is preferred transiting to the time base timer or the timer mode Data hold function In th...

Страница 115: ...CR it executes the interrupt handling When CPU is not ready to accept an interrupt it executes the interrupt handling from the instruction next to the one specifying Figure 5 5 shows the cancellation of sleep mode by an interrupt Fig 5 5 Cancellation of Sleep Mode by Interrupt Note At interrupt handling the CPU usually proceeds to the interrupt handling after executing the instruction next to the ...

Страница 116: ...register LPMCR controls whether to set the external pin to the immediately preceding state or to the high impedance state in the time base timer mode n Cancellation of time base timer mode The low power consumption controller cancels the time base timer mode at a reset input or a generation of interrupt issuance Return by a reset At a reset time base timer is initialized to the main clock mode Ret...

Страница 117: ... reset input or a generation of interrupt Return by areset When the watch mode is cancelled by a reset factor the timer mode is cancelled and then the oscillation stabilization wait reset state occurs The reset sequence is executed after the oscillation stabilization wait time has elapsed Return by an interrupt When an interrupt request with a higher interrupt level than 7 is issued from a resourc...

Страница 118: ...5 6 gives a cancellation of timer mode external reset Fig 5 6 Cancellation of Timer Mode External Reset Timer mode PLL clock CPU clock Main clock Reset sequence Oscillation stabilization wait Cancellation of reset Cancellation of timer mode Stopped Stopped Oscillating Processing Oscillating ...

Страница 119: ...p mode Return by a reset When the stop mode is cancelled by a reset factor the stop mode is cancelled and then the oscillation stabilization wait reset state occurs The reset sequence is executed after the oscillation stabilization wait time has elapsed Return by an interrupt When an interrupt request higher interrupt level than 7 is issued from a resource during the stop mode the interrupt contro...

Страница 120: ...ws the return operation from the stop mode Fig 5 7 Cancellation of Stop Mode External Reset PST pin Stop mode Main clock PLL clock CPU clock CPU operation Main clock Reset sequence Oscillation stabilization wait Cancellation of reset Cancellation of stop mode Stopped Stopped Oscillating Processing ...

Страница 121: ...ware reset End of oscillation stabilization wait End of oscillation stabilization wait SLP 1 TMD 0 STP 1 interrupt interrupt interrupt SLP 1 TMD 0 STP 1 interrupt interrupt interrupt Time base timer mode MCS 1 MCS 0 Lowering of power supply voltage Low voltage detection reset Sub clock mode Sub sleep mode Sub stop mode SLP 1 TMD 0 STP 1 interrupt interrupt interrupt Timer mode Main clock oscillati...

Страница 122: ... Stop Stop PLL Oscillation stabilization wait Operate Operate Operate Stop Stop Operate Operate PLL clock Main Operate Main sleep Operate Time base timer Operate Operate Operate Operate Main stop Stop Stop Stop Stop Main oscillation stabilization wait Operate Operate Stop Stop Stop Operate Operate Main clock Sub Operate Sub sleep Operate Timer Operate Operate Sub stop Stop Stop Sub oscillation sta...

Страница 123: ...tate in which the input function enabled Consequently the pull up pull down option needs to be selected or external input needs to be performed When the pins are used as output port pins they are the same as the pins of other ports 2 This means that holding the output state preceding this mode However when that state is the input state input is disabled Holding the output state preceding this mode...

Страница 124: ... time base timer mode or stop mode This operation is performed irrespective of whether the interrupt request is accepted by the CPU After cancellation of standby mode a branch is caused to the interrupt processing routine as an normal interrupt processing under the following conditions the priority specified for the interrupt level setting bits ICR IL2 IL1 IL0 corresponding to the interrupt reques...

Страница 125: ...CR Setting 00B to the WS1 and WS0 bits is allowed only in the main clock mode Oscillation stabilization wait time for PLL clock At a transition from a mode in which the CPU is operating on the main clock and the PLL clock is stopped to a mode in which the CPU or a resource operates on the PLL clock a transition is performed to the PLL clock oscillation stabilization wait state in which the CPU or ...

Страница 126: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 5 24 ...

Страница 127: ...6 3 Interrupt Control Registers and Resources 6 7 6 4 Hardware Interrupt 6 13 6 5 Software Interrupt 6 21 6 6 EI2 OS Interrupt 6 23 6 7 Exception Handling Interrupt 6 33 6 8 Stack Operation for Interrupt Handling 6 34 6 9 Program Example for Interrupt Handling 6 36 6 INTERRUPT ...

Страница 128: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 6 2 ...

Страница 129: ...ser by executing an instruction such as INT instruction dedicated to the software interrupt Interrupt by expansion intelligent I O service EI 2 OS The EI 2 OS transfers data automatically between the resource and memory The EI 2 OS enables data transfer conventionally used for a interrupt processing program to be performed in the same manner as DMA direct memory access When the data transfer is co...

Страница 130: ...ack Save dedicated registers to system stack EI2 OS Update CPU interrupt processing level ILM String family instruction executing YES NO YES NO YES Return to dedicated registers from system stack call interrupt routine and return to previous routine Return processing due to interrupt YES NO Interrupt determination is performed by the step during execution of string family instruction Main program ...

Страница 131: ...OS exception handling hardware interrupt and software interrupt Table 6 1 shows the interrupt number and allocation of interrupt vector Table 6 1 Interrupt Vectors Software Interrupt Instruction Vector Address L Vector Address M Vector Address H Mode Data Interrupt No Hardware Interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Unused 0 None INT7 FFFFE0H FFFFE1H FFFFE2H Unused 7 None INT8 FFFFDCH FFFFDDH FFFFD...

Страница 132: ...n 24 18H FFFF9CH ICR06 0000B6H 1 PPG timer 0 25 19H FFFF98H DTP external interrupt at channel 6 7 detection 26 1AH FFFF94H ICR07 0000B7H 1 PPG timer 1 27 1BH FFFF90H Reload timer 1 28 1CH FFFF8CH ICR08 0000B8H 1 PPG timer 2 29 1DH FFFF88H Watch timer main clock 30 1EH FFFF84H ICR09 0000B9H 1 Free run timer over flow 31 1FH FFFF80H End of conversion by A D converter 32 20H FFFF7CH ICR10 0000BAH 1 C...

Страница 133: ...7H Interrupt control register 07 ICR07 PPG timer 0 DTP external interrupt 6 7 0000B8H Interrupt control register 08 ICR08 PPG timer 1 reload timer 1 0000B9H Interrupt control register 09 ICR09 PPG timer 2 watch timer main clock 0000BAH Interrupt control register 10 ICR10 Free run timer A D converter 0000BBH Interrupt control register 11 ICR11 Free run timer sound generator 0000BCH Interrupt contro...

Страница 134: ...CS1 ICS0 ISE IL2 IL1 IL0 MSB LSB 00000111B Initial value IL2 IL1 IL0 Interrupt Level Setting Bit 0 0 0 Interrupt level 0 highest 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 7 no interrupt ISE EI2 OS Enable Bit 0 The interrupt sequence is started at an interrupt 1 EI2 OS is started at an interrupt EI2 OS Channel Select Bits ICS3 ICS2 ICS1 ICS0 Channel Descriptor Address 0 0 0 0 0 0001...

Страница 135: ...evel Setting Bit 0 0 0 Interrupt level 0 highest 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 7 no interrupt ISE EI2 OS Enable Bit 0 The interrupt sequence is started at an interrupt 1 EI2 OS is started at an interrupt S1 S0 EI2 OS Status 0 0 When EI2 OS in operation or not started 0 1 Stop state by end of counting 1 0 Reserved 1 1 Stop state by request issued from resource At read 00...

Страница 136: ... ICR Fig 6 4 Configuration of Interrupt Control Register ICR Remarks 1 The ICS3 to ICS0 bits are only enabled at starting the EI2 OS When starting EI2 OS set the ISE bit to 1 when not starting EI2 OS set the ISE bit to 0 When not starting EI2 OS the ICS3 to ICS0 bits need not be set 2 ICS1 and ICS0 are only enabled at writing and S1 and S0 are only enabled at reading At write to interrupt control ...

Страница 137: ...ing Bits and Interrupt Levels IL2 IL1 IL0 Interrupt Level 0 0 0 0 Highest 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 6 Lowest 1 1 1 7 No interrupt EI 2 OS Enable bit ISE EI 2 OS is started when this bit is 1 at an interrupt request issuance When this bit is 0 at an interrupt request issuance the interrupt sequence is started Also the ISE bit is cleared when the EI 2 OS termination condition is satisfied ...

Страница 138: ...0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H EI 2 OS Status bits S1 and S0 These are read only bits The operation state or termination state can be identified by comparing t...

Страница 139: ... is not be started in the multiple mode during processing of a certain EI 2 OS other interrupt requests and EI 2 OS requests are all suspended External interrupt The external interrupt wake up interrupt included is accepted as a hardware interrupt by means of the resource interrupt request detector Interrupt vector The interrupt vector tables referred during interrupt handling are allocated to FFF...

Страница 140: ... Register Area Hardware interrupt inhibition by interrupt inhibit instruction The ten hardware interrupt inhibit instructions shown in Table 6 8 do not detect the existence of hardware interrupt request and they ignore the hardware interrupt request When a valid hardware interrupt request is issued during execution of these instructions interrupt handling is performed for the interrupt request onl...

Страница 141: ...ling The CPU compares the received interrupt level ICR IL2 to IL0 and the interrupt level mask register ILM and starts the interrupt handling microcode after termination of the currently executing instruction when IL ILM and the interrupt is enabled PS CCR I 1 The CPU refers the ISE bit of the interrupt control register ICR at the beginning of the interrupt handling microcode and continues the int...

Страница 142: ...son when the priority of the interrupt processing level is higher than that of the current interrupt processing level the CPU checks the value of the I flag in the condition code register CCR 6 When result of the check in 5 above shows that the I flag indicates interrupt enable I 1 completion of the currently executing instruction is awaited and at completion the requested interrupt level IL is se...

Страница 143: ...l mask register in PS I IF IE 1 AND ILM IL START INT Instruction Fetch and decode next instruction RETI Instruction Repetitive execution of string family instruction completed ISE 1 Move pointer to next instruction by updating PC I 0 Disable hardware interrupt Software interrupt or exception handling Save dedicated registers to system stack Save dedicated registers to system stack EI2 OS YES NO YE...

Страница 144: ... acceptable state 6 A hardware interrupt request issued when an interrupt occurs in the resource 7 In the interrupt handling hardware the registers are saved and branch to the interrupt processing program 8 Resource is processed for generation of interrupt by the interrupt processing program 9 An interrupt request to the resource is cleared 10 The interrupt return instruction is executed to return...

Страница 145: ...ring processing of EI 2 OS other interrupt requests and other EI 2 OS requests are all held Example of multiple interrupt As an example of the multiple interrupt handling it is assumed that the timer interrupt is preferred to the A D converter interrupt so the interrupt level of the A D converter is set to 2 and the interrupt level of the timer is set to 1 In this case when a timer interrupt occur...

Страница 146: ...pt request is issued immediately after starting execution of the POPW RW0 RW7 instructions with the longest execution cycle 45 machine cycles Interrupt handling time θ machine cycles The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the system stack and fetch the interrupt vectors after accepting the interrupt request The interrupt handling time is ...

Страница 147: ...updated During execution of the INT instruction the I flag of the condition code register CCR is set to 0 to mask the hardware interrupt To enable the hardware interrupt during software interrupt handling set the I flag to 1 in the software interrupt processing routine Operation of software interrupt When the CPU fetches and executes the INT instruction the microcode for software interrupt handlin...

Страница 148: ...sters according to the microcode corresponding to the software interrupt instruction branch processing is performed 3 The interrupt handling is terminated by the RETI instruction in the interrupt processing routine of user Note When the program bank register PCB is FFH the vector area for the CALLV instruction overlaps the table for the INT vct8 instruction A CALLV and INT vct8 instructions can no...

Страница 149: ...te of the resource I O transfer of unnecessary data is not required No increment nor update can be selected for the buffer address No increment nor update can be selected for the I O register address Termination interrupt by EI 2 OS When data transfer by EI 2 OS terminates termination conditions are set to S1 and S0 of the interrupt control register to branch to the interrupt processing routine au...

Страница 150: ... Transfer source and destination are read from descriptor 4 Transfer between I O and memory is executed 5 Interrupt factor is cleared automatically I O Register ISD Buffer Memory space ISD EI2 OS descriptor IOA I O address pointer BAP Buffer address pointer ICS EI2 OS channel select bit of ICR DCT Data counter Resource I O I O register 5 1 Interrupt control register ICR 2 3 By DCT 4 CPU 3 By IOA B...

Страница 151: ...rrespondence between Channel Number and Descriptor Address Channel Descriptor Address 0 000100H 1 000108H 2 000110H 3 000118H 4 000120H 5 000128H 6 000130H 7 000138H 8 000140H 9 000148H 10 000150H 11 000158H 12 000160H 13 000168H 14 000170H 15 000178H MSB Upper 8 bits of data counter DCTH Lower 8 bits of data counter DCTL Upper 8 bits of I O register address pointer IOAH Lower 8 bits of I O regist...

Страница 152: ... 16 bit length register to transfer data with the buffer The register indicates the lower addresses A15 to A0 of the I O register The upper addresses A23 to A16 are all 0s This register can be used to specify any I O register at addresses 000000H to 00FFFFH Figure 6 15 shows the configuration of IOA Fig 6 15 Configuration of I O Register Address Pointer IOA B15 B14 B04 B05 B06 B01 B07 B02 B08 B09 ...

Страница 153: ...t 2 bit 1 bit 0 R W R W R W R W R W R W R W R W XXXXXXXXB Initial value SE EI2 OS Termination Control Bit 0 EI2 OS is not terminated by a request from resource 1 EI2 OS is terminated by a request from resource DIR Data Transfer Direction Specification Bit 0 I O Register address pointer Buffer address pointer 1 Buffer address pointer I O register address pointer BF BAP Updating Fixing Selection Bit...

Страница 154: ...ndicates updating BAP changes only in the lower 16 bits BAPH BAPL and does not change in the upper 8 bits BAPH Figure 6 17 shows the configuration of the buffer address pointer BAP Fig 6 17 Configuration of Buffer Address Pointer BAP Remarks 1 The area that can be specified by the I O address pointer IOA is 000000H to 00FFFFH 2 The area that can be specified by the buffer address pointer BAP is 00...

Страница 155: ...o CPU operation Interrupt sequence Updating value depends on BW YES SE 1 Update IOA Update BAP Set S1 and S0 to 01 Set S1 and S0 to 11 Clear ISE to 0 Interrupt sequence NO NO NO NO NO NO YES YES YES YES YES YES NO Updating value depends on BW EI2 OS termination processing ISD EI2 OS descriptor ISCS EI2 OS status register IF IOA updating fixing selection bit of EI2 OS status register ISCS BW Transf...

Страница 156: ...nting out or a termination request from resources Processing data in buffer Reset EI2 OS channel switching RETI Set system stack area Set EI2 OS descriptor Initialize resources Set interrupt control register ICR Set start operation of internal resource and interrupt enable bit Set ILM and I in PS Execute user program Start Initial setting S1 S0 00 Interrupt request and ISE 1 Branch to interrupt ve...

Страница 157: ...Setting of EI 2 OS Termination Control Bit SE Termination by Termination Request from Resource Ignores Termination Request from Resource Setting of IOA Updating Fixing Selection Bit IF Fixed Updated Fixed Updated Fixed 32 34 33 35 Setting of BAP address updating fixing selection bit BF Updated 34 36 35 37 Unit Machine cycle one machine cycle is equal to one cycle of the machine clock φ In addition...

Страница 158: ...ling time Table 6 13 Compensation Value Z for Interrupt Handling Time Address Indicated by Stack Pointer Compensation Value Z External area 8 bit address 4 External area even address 1 External area odd address 4 Internal area even address 0 Internal area odd address 2 At termination by termination request from resource I O When the EI 2 OS data transfer is terminated ICR S1 SO 11 on the way by th...

Страница 159: ... exception handling the following processing is performed before branching the control to the interrupt processing routine The A DPR ADB DTB PCB PC and PS registers are saved in the system stack The I flag of the condition code register CCR is cleared to 0 and mask the hardware interrupt The S flag of the condition code register CCR is set to 1 and validate the system stack The value of the progra...

Страница 160: ...e following order 1 Accumulator A 2 Direct page register DPR 3 Additional data bank register ADB 4 Data bank register DTB 5 Program bank register PCB 6 Program counter PC 7 Processor status PS Figure 6 20 shows the stack operation at starting interrupt handling Fig 6 20 Stack Operation at Starting Interrupt Handling Byte Just after interrupt SSB 00H 08F2H SSP A AH AL 0000H 08FEH DPR 01H ADB 00H DT...

Страница 161: ...ther with the data area in RAM Figure 6 21 shows the stack area Fig 6 21 Stack Area Notes 1 When setting addresses in the stack pointers SSP USP in principle set even addresses 2 Place the system stack area user stack area and data area not to be overlapped one another System stack and user stack Use the system stack area for interrupt handling When the user stack area is used at issuance of inter...

Страница 162: ... 0 The general purpose register uses the starting bank MOV ILM 07H ILM in PS set to level 7 MOV A STACK_T System stack set MOV SSB A MOVW A STACK_T Stack pointer set MOVW SP A In this case S flag 1 so SSP set MOV DDR1 00000000B The P10 INT0 pin is set to input OR CCR 40H I flag of CCR in PS set to enable the interrupt MOV I ICR00 00H Interrupt level 0 highest MOV I ELVR 00000001B INT0 as an H leve...

Страница 163: ... counter DCTH EQU 000107H Upper of data counter ERO EQU EIRR 0 External interrupt request flag bit defined STACK SSEG Stack RW 100 STACK_T RW 1 STACK ENDS Main program CODE CSEG START AND CCR 0BFH I flag of CCR in PS cleared to disable interrupt MOV RP 00 Register bank pointer set MOV A STACK_T System stack set MOV SSB A MOVW A STACK_T Stack pointer set MOVW SP A In this case S flag 1 so SSP set M...

Страница 164: ... Interrupt DTP request flag cleared Processing by user EI2OS termination factor checked buffer data processed EI2OS re set RETI CODE ENDS Vector setting VECT CSEG ABS OFFH ORG OFFDOH Vector set to interrupt 11 0BH DSL WARI ORG OFFDCH Reset vector setting DSL START DB 00H Set to single chip mode VECT ENDS END START ...

Страница 165: ...7 1 Mode Setting 7 3 7 2 Mode Pins MD2 to MD0 7 4 7 3 Mode Data 7 5 7 MODE SETTING ...

Страница 166: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 7 2 ...

Страница 167: ...n mode the normal operation can be started Note In the MB90420 5 A series only the single chip mode is used so set MD2 MD1 and MD0 to 011 and set M1 and M0 to 00 n Bus mode The bus mode controls the operation of the internal ROM and external access functions and is specified by the mode setting pins MDx and the value of Mx bit in mode data The mode setting pins MDx specify the bus mode when the re...

Страница 168: ...lit in product the mode pins also specify the FLASH ROM writing mode to write programs to internal ROM The setting of the mode pins is shown in Table 7 1 Table 7 1 Setting of Mode Pins MD2 MD1 MD0 Mode Name Reset Vector Access Area External Data Bus Width Remarks 0 0 0 0 0 1 0 1 0 Setting disabled 0 1 1 Internal vector mode Internal Mode data Operation after reset sequence is controlled by mode da...

Страница 169: ...ata setting is valid after the reset sequence Figure 7 2 shows the configuration of mode data 7 5 4 3 2 1 0 Mode data M1 0 0 0 0 0 0 Bus mode setting bits Function expansion bits reserved area Fig 7 2 Configuration of Mode Data n Bus mode setting bits The bus mode setting bits specify the operation mode after completion of the reset sequence Table 7 2 shows the relationship between each bit and th...

Страница 170: ...ach product Fig 7 3 Relationship between Access Areas and Physical Addresses in Single chip Mode n Relationships between mode pins and mode data Table 7 3 shows the relationships between mode pins and mode data Table 7 3 Relationships between Mode Pins and Mode Data Mode MD2 MD1 MD0 M1 M0 Single chip mode 0 1 1 0 0 Note In the MB90420 5 A series only the single chip mode is used ROM ROM Internal a...

Страница 171: ...d Assignment of Pins Serving as External Pins 8 5 8 3 Port 0 8 6 8 4 Port 1 8 11 8 5 Port 3 8 16 8 6 Port 4 8 21 8 7 Port 5 8 26 8 8 Port 6 8 31 8 9 Port 7 8 36 8 10 Port 8 8 41 8 11 Port 9 8 46 8 12 Program Example Using I O Ports 8 51 8 I O PORT ...

Страница 172: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 8 2 ...

Страница 173: ... each port and the resources that it also serves as Port 0 Serves as both general purpose I O port and resource External interrupt input pin UART PPG Port 1 Serves as both general purpose I O port and resource PPG reload timer watch timer ICU Port 3 Serves as both general purpose I O port and resource LCD Port 4 Serves as both general purpose I O port and resource LCD Port 5 Serves as both general...

Страница 174: ...6 SEG 15 SEG 14 General purpose I O port P57 P56 P55 P54 P53 P52 P51 P50 SGA SGO RX0 TX0 INT3 INT2 INT1 INT0 Port 5 P50 INT0 to P57 SGA CMOS hysteresis Resource TX1 RX1 General purpose I O port P67 P66 P65 P64 P63 P62 P61 P60 Port 6 P60 AN0 to P67 AN7 Analog CMOS hysterisys Resource AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 General purpose I O port P77 P76 P75 P74 P73 P72 P71 P70 Port 7 P70 PWM1 P0 to P77 P...

Страница 175: ...register PDR6 R W 000006H XXXXXXXXB Port 7 data register PDR7 R W 000007H XXXXXXXXB Port 8 data register PDR8 R W 000008H XXXXXXXXB Port 9 data register PDR9 R W 000009H XXB Port 0 direction register DDR0 R W 000010H 00000000B Port 1 direction register DDR1 R W 000011H 000000B Port 3 direction register DDR3 R W 000013H 00 B Port 4 direction register DDR4 R W 000014H 00000000B Port 5 direction regi...

Страница 176: ...e I O pins resource I O pins P00 SIN0 INT4 to P07 PPG1 Port 0 data register PDR0 Port 0 direction register DDR0 n Pins of port 0 The pins of the port 0 also serve as resource I O pins so when using a pin of port 0 as a resource I O pin it cannot be used as a general purpose I O port Table 8 3 shows the pins of port 0 Table 8 3 Pins of Port 0 I O Type Port Name Pin Name Port Function Resouce Input ...

Страница 177: ... correspondence between the registers and pins for port 0 Table 8 4 Correspondence between Registers and Pins for Port 0 Port Name Bits of Related Registers and Corresponding Pins PDR0 DDR0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Port 0 Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00 Internal data bus PDR port data register PDR read PDR write Output latch DDR port direction register Dire...

Страница 178: ...resource irrespective of the value of the DDR0 register When using a resource with input pins write 0 to the bits of the DDR0 register that correspond to the input pins of each resource to set those input pins as input ports Table 8 5 Function of Registers for Port 0 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and wh...

Страница 179: ...in is set to the high impedance state When data is written to the PDR0 register data is held at the output latch in PDR but not output to the pin When the PDR0 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin When using a pin as a the resource output pin set the output enable bit for At I O switching the output enable bit for a resource is p...

Страница 180: ...tput buffer is set forcibly to OFF irrespective of the value of the DDR0 register Input is fixed to prevent leakage due to opening of input Table 8 6 State of Port 0 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P00 SIN0 INT4 to P07 PPG1 General purpose I O port pin General purpose I O port pin General purpose I O port pin...

Страница 181: ...pt input pins P10 PPG2 to P15 INT0 Port 1 data register PDR1 Port 1 direction register DDR1 n Pins of port 1 The pins of the port 1 also serve as resource I O pins so when using a pin of port 1 as a resource I O pin it cannot be used as a general purpose I O port Table 8 7 shows the pins of port 1 Table 8 7 Pins of Port 1 I O Type Port Name Pin Name Port Function Resouce Input Output Circuit Type ...

Страница 182: ... 1 1 to 1 Table 8 8 shows the correspondence between the registers and pins of port 1 Table 8 8 Correspondence between Registers and Pins for Port 1 Port Name Bits of Related Registers and Corresponding Pins PDR1 DDR1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Port 1 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 Internal data bus PDR port data register PDR read PDR write Output latc...

Страница 183: ...e of the DDR1 register When using a resource with input pins write 0 to the bits of the DDR1 register that correspond to the input pins of the resource to set those input pins as input ports Table 8 9 Function of Registers for Port 1 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and when the pin is an output port pin t...

Страница 184: ...ut buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR1 register data is held at the output latch in PDR but not output to the pin When the PDR1 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin When using a pin as a resource output pin set the output enable bit for resource At I O switching the...

Страница 185: ... value of the DDR1 register Input is fixed to prevent leakage due to opening of input Table 8 10 shows the state of the port 1 pins Table 8 10 State of Port 1 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P10 PPG2 to P15 IN0 General purpose I O port pin General purpose I O port pin General purpose I O port pin Input cut of...

Страница 186: ...of port 3 Port 3 consists of the following three elements General purpose I O pins resource I O pins P36 SEG12 to P37 SEG13 Port 3 data register PDR3 Port 3 direction register DDR3 n Pins of port 3 The pins of the port 3 also serve as resource I O pins so when using a pin of port 3 as a resource I O pin it cannot be used as a general purpose I O port Table 8 11 shows the pins of port 3 Table 8 11 ...

Страница 187: ...e 8 12 shows the correspondence between the registers and the pins of port 3 Table 8 12 Correspondence between Registers and Pins for Port 3 Port Name Bits of Related Registers and Corresponding Pins PDR3 DDR3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Port 3 Corresponding pin P37 P36 Internal data bus PDR port data register PDR read PDR write Output latch DDR port direction register Di...

Страница 188: ...rce that corresponds to the pin is set the pin is forcibly set as an output pin of the resource irrespective of the value of the DDR3 register Table 8 13 Function of Registers for Port 3 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and when the pin is an output port pin the L level is output to the pin Port 3 data reg...

Страница 189: ...R3 register is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR3 register data is held at the output latch in PDR but not output to the pin When the PDR3 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin W...

Страница 190: ...rcibly to OFF irrespective of the value of the DDR3 register Input is fixed to prevent leakage due to opening of input Table 8 14 shows the state of the port 3 pins Table 8 14 State of Port 3 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P36 SEG12 to P37 SEG13 General purpose I O port pin General purpose I O port pin Gener...

Страница 191: ...pins P40 SEG14 to P47 SEG15 Port 4 data register PDR4 Port 4 direction register DDR4 n Pins of port 4 The I O pins of the port 4 also serve as resource I O pins so when using a pin of port 4 as a resource I O pin it cannot be used as a general purpose I O port Table 8 15 shows the pins of port 4 Table 8 15 Pins of Port 4 I O Type Port Name Pin Name Port Function Resource Input Output Circuit Type ...

Страница 192: ...for port 4 are PDR4 and DDR4 The bits composing each register correspond to the pins of port 4 1 to 1 Table 8 16 shows the correspondence between the registers and the pins of port 4 Table 8 16 Correspondence between Registers and Pins for Port 4 Port Name Bits of Related Registers and Corresponding Pins PDR4 DDR4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Port 4 Corresponding pin P47 P46 P45...

Страница 193: ...t the pin is forcibly set as an output pin of each resource irrespective of the value of the DDR4 register Table 8 17 Function of Registers for Port 4 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and when the pin is an output port pin the L level is output to the pin Port 4 data register PDR4 1 The pin state is H leve...

Страница 194: ...When the bit of the corresponding DDR4 register is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR4 register data is held at the output latch in PDR but not output to the pin When the PDR4 register is read the level value 0 or 1 of the pin is read Operation wh...

Страница 195: ...value of the DDR4 register Input is fixed to prevent leakage due to opening of input Table 8 18 shows the state of the port 4 pins Table 8 18 State of Port 4 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P40 SEG14 to P47 SEG21 General purpose I O port pin General purpose I O port pin General purpose I O port pin Input cut ...

Страница 196: ...ns resource input pins P50 INT0 to P57 SGA Port 5 data register PDR5 Port 5 direction register DDR5 n Pins of port 5 The I O pins of the port 5 also serve as resource input pins so when using a pin of port 5 as a resource I O pin it cannot be used as a general purpose I O port Table 8 19 shows the pins of port 5 Table 8 19 Pins of Port 5 I O Type Port Name Pin Name Port Function Resouce Input Outp...

Страница 197: ...ondence between the registers and the pins for port 5 Table 8 20 Correspondence between Registers and Pins for Port 5 Port Name Bits of Related Registers and Corresponding Pins PDR5 DDR5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Port 5 Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50 Internal data bus PDR port data register PDR read PDR write Output latch DDR port direction register D...

Страница 198: ...irrespective of the value of the DDR5 register When using a resource with input pins set 0 to the bits of the DDR5 register that correspond to the input pins of each resource to set those input pins as input ports Table 8 21 Function of Registers for Port 5 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and when the pin...

Страница 199: ...et to the high impedance state When data is written to the PDR5 register data is held at the output latch in PDR but not output to the pin When the PDR5 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin When using a pin as a resource output pin set the output enable bit for the resource At I O switching the output enable bit for a resource is...

Страница 200: ...orcibly to OFF irrespective of the value of the DDR5 register Input is fixed to prevent leakage due to opening of input Table 8 22 shows the state of the port 5 pins Table 8 22 State of Port 5 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P50 INT0 to P57 SGA General purpose I O port pin General purpose I O port pin General...

Страница 201: ...register ADER n Pins of port 6 The I O pins of the port 6 also serve as analog input pins so when using a pin of port 6 as an analog input pin it cannot be used as a general purpose I O port Also when using the pin as a general purpose port do not use it as an analog input pin Table 8 23 shows the pins of port 6 Table 8 23 Pins of Port 6 I O Type Port Name Pin Name Port Function Resource Input Out...

Страница 202: ...rresponds to the pin In this case the value read from the PDR6 register is 0 n Registers for port 6 The registers for port 6 are PDR6 DDR6 and ADER The bits composing each register correspond to the pins of port 6 1 to 1 Table 8 24 shows the correspondence between the registers and the pins for port 6 Table 8 24 Correspondence between Registers and Pins for Port 6 Port Name Bits of Related Registe...

Страница 203: ...urrent flows So when using a pin as an analog input pin always set the corresponding bit of ADER to analog input Remark At a reset DDR6 is initialized to 0 and the ADER register is initialized to 1 and the analog input mode occurs Table 8 25 Function of Registers for Port 6 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level When DDR6 is set to 0 the hig...

Страница 204: ...tching a bit that is used as input to output write the output data to the PDR register and then set the DDR register to output Operation at input port When the bit of the corresponding DDR6 register is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR6 register ...

Страница 205: ... OFF Input is fixed to prevent leakage due to opening of input Table 8 26 shows the state of the port 6 pins Table 8 26 State of Port 6 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P60 AN0 to P67 AN7 General purpose I O port pin General purpose I O port pin General purpose I O port pin Input cut off and output becomes Hi ...

Страница 206: ...s resource I O pins P70 PWM1P0 to P77 PWM2M1 Port 7 data register PDR7 Port 7 direction register DDR7 n Pins of port 7 The I O pins of the port 7 also serve as resource I O pins so when using a pin of port 7 as a resource I O pin it cannot be used as a general purpose I O port Table 8 27 shows the pins of port 7 Table 8 27 Pins of Port 7 I O Type Port Name Pin Name Port Function Resource Input Out...

Страница 207: ...ing each register s bits correspond to the pins of port 7 1 to 1 Table 8 28 shows the correspondence between the registers and the pins for port 7 Table 8 28 Correspondence between Registers and Pins for Port 7 Port Name Bits of Related Registers and Corresponding Pins PDR7 DDR7 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Port 7 Corresponding pin P77 P76 P75 P74 P73 P72 P71 P70 Internal ...

Страница 208: ... each resource that corresponds to the pin is set the pin is forcibly set as an output pin of the resource irrespective of the value of the DDR0 register Table 8 29 Function of Registers for Port 7 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and at the output port the L level is output to the pin Port 7 data register...

Страница 209: ...gister is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR7 register data is held at the output latch in PDR but not output to the pin When the PDR7 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin When u...

Страница 210: ...cibly to OFF irrespective of the value of the DDR7 register Input is fixed to prevent leakage due to opening of input Table 8 30 shows the state of the port 7 pins Table 8 30 State of Port 7 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P70 PWM1P0 to P77 PWM2M1 General purpose I O port pin General purpose I O port pin Gene...

Страница 211: ...P87 PWM2M3 Port 8 data register PDR8 Port 8 direction register DDR8 n Pins of port 8 The I O pins of the port 8 also serve as resource I O pins so when using a pin of port 8 as a resource I O pin it cannot be used as a general purpose I O port Table 8 31 shows the pins of port 8 Table 8 31 Pins of Port 8 I O Type Port Name Pin Name Port Function Resource Input Output Circuit Type P80 PWM1P2 P80 PW...

Страница 212: ...rt 8 are PDR8 and DDR8 The bit composing each register s bits correspond to the pins of port 8 1 to 1 Table 8 32 shows the correspondence between the registers and the pins for port 8 Table 8 32 Correspondence between Registers and Pins for Port 8 Port Name Bits of Related Registers and Corresponding Pins PDR8 DDR8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Port 8 Corresponding pin P87 P86 P8...

Страница 213: ...o the pin is set the pin is forcibly set as an output pin of the resource irrespective of the value of the DDR0 register Table 8 33 Function of Registers for Port 8 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and at the output port the L level is output to the pin Port 8 data register PDR8 1 The pin state is H level ...

Страница 214: ...e bit of the corresponding DDR8 register is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR8 register data is held at the output latch in PDR but not output to the pin When the PDR8 register is read the level value 0 or 1 of the pin is read Operation when pin ...

Страница 215: ...alue of the DDR8 register Input is fixed to prevent leakage due to opening of input Table 8 34 shows the state of the port 8 pins Table 8 34 State of Port 8 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P80 PWM1P2 to P87 PWM2M3 General purpose I O port pin General purpose I O port pin General purpose I O port pin Input cut...

Страница 216: ...t 9 Port 9 consists of the following three elements General purpose I O pins resource I O pin P90 SEG22 to P91 SEG23 Port 9 data register PDR9 Port 9 direction register DDR9 n Pins of port 9 The I O pins of the port 9 also serve as resource I O pins so when using a pin of port 9 as a resource I O pin it cannot be used as a general purpose I O port Table 8 35 shows the pins of port 9 Table 8 35 Pin...

Страница 217: ... The bits composing each register correspond to the pins of port 9 1 to 1 Table 8 3 shows the correspondence between the registers and the pins for port 9 Table 8 36 Correspondence between Registers and Pins for Port 9 Port Name Bits of Related Registers and Corresponding Pins PDR9 DDR9 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Port 9 Corresponding pin P91 P90 Internal data bus PDR por...

Страница 218: ...nds to the pin is set the pin is forcibly set as an output pin of the resource irrespective of the value of the DDR0 register Table 8 37 shows the function of the port 9 pin registers Table 8 37 Function of Registers for Port 9 Register Name Data At Read At Write Read Write Address Initial Value 0 The pin state is L level 0 is set for the output latch and at the output port the L level is output t...

Страница 219: ...gister is set to 0 the pin becomes an input port pin When the pin is an input port pin the output buffer is set to OFF and the pin is set to the high impedance state When data is written to the PDR9 register data is held at the output latch in PDR but not output to the pin When the PDR9 register is read the level value 0 or 1 of the pin is read Operation when pin used as resource output pin When u...

Страница 220: ...rcibly to OFF irrespective of the value of the DDR9 register Input is fixed to prevent leakage due to opening of input Table 8 38 shows the state of the port 9 pins Table 8 38 State of Port 9 Pins Pin Name Normal Operation Sleep Mode Stop Mode or Time base Timer Mode SPL 0 Stop Mode or Time base Timer Mode SPL 1 P90 SEG22 to P91 SEG23 General purpose I O port pin General purpose I O port pin Gener...

Страница 221: ...g specification All seven segment eight segment when Dp included LEDs turned on using port 0 and port 1 P00 pin corresponds to common anode pin of LED and P10 to P17 pins correspond to segment pins An eight segment LED connection example is shown below Fig 8 10 Eight segment LED Connection Example MB90420 series P10 P07 P06 P05 P04 P03 P02 P01 P00 ...

Страница 222: ... EQU 000001H DDR0 EQU 000010H DDR1 EQU 000011H Main program CODE CSEG START Initialized MOV I PDR1 00000000B PI0 set to L level XXXXXXXOB MOV I DDR1 11111111B All bits for port 1 pins set to output MOV I PDR0 11111111B All bits for port 0 1 MOV I DDR0 11111111B All bits for port 0 pins set to output ENDS CODE END START ...

Страница 223: ...mer 9 4 9 3 List of Watchdog Timer Time base Timer and Watch Timer Registers 9 5 9 4 Operation of Watchdog Timer Time base Timer and Watch Timer 9 11 9 5 Precautions at Using Watchdog Timer and Time base Timer 9 17 9 6 Program Examples of Watchdog Timer and Time base Timer 9 19 9 WATCHDOG TIMER TIME BASE TIMER WATCH TIMER SUB CLOCK ...

Страница 224: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 9 2 ...

Страница 225: ...control unit When the watchdog timer is not cleared within a certain period of timer after being started the CPU is reset Time base timer function The time base timer is an 18 bit free run counter time base counter that increments in synchronization with the internal count clock 2 divided original oscillation and has an interval timer function that can be selected from four types of interval times...

Страница 226: ... Selector Time base timer 2 divided main original oscillation Clock input 211 213 215 218 TBTRES 211 213 215 218 TBR TBIE TBOF AND S Q R Time base interrupt Selector WT1 WT0 WTE WDTC 2 bit counter CLR OF Watchdog reset generation circuit CLR WDGRST To internal reset generation circuit WTC WTC2 to WTC0 Selector Watch timer Clock input 28 29 210 211 212 213 214 215 WTRES 210 213 214 215 WDCS SCE WTR...

Страница 227: ...trol register 7 6 5 4 3 2 1 0 Bit No Address 0000A8H PONR WRST ERST SRST WTE WT1 WT0 WDTC Read write R R R R W W W Initial value X X X X 1 1 1 Time base timer contol register 15 14 13 12 11 10 9 8 Bit No Address 0000A9H Reserved TBIE TBOF TBR TBC1 TBC0 TBTC Read write R W R W W R W R W Initial value 1 0 0 1 0 0 Watch timer control register 7 6 5 4 3 2 1 0 Bit No Address 0000AAH WDCS SCE WTIE WTOF ...

Страница 228: ...eset factors except at power on are not assured So create the software so as to ignore other bits when the PONR bit is 1 Table 9 1 PONR STBR WRST ERST SRST Reset Factor Bits Reset Factor PONR WRST ERST SRST Power on 1 Watchdog timer 1 External pin RSTX input 1 RST bit software reset 1 The previous value is held This register value is not assured when power is risen when no power on reset occurs bi...

Страница 229: ... input clock of the watchdog timer when WDCS is set to 1 when the sub clock is selected as the machine clock the output of the watch timer can be selected as the input clock of the watchdog timer Table 9 2 gives the setting of the interval time based on the WT1 and 0 bits Table 9 2 WT1 and 0 Interval Time Select Bits Interval Time Original Oscillation 4 MHz WDCS SCM WT1 WT0 Minimum Maximum 1 0 0 A...

Страница 230: ...red by writing 0 to TBOF transitions to the stop mode transitions from the sub clock mode to the main clock mode transitions from the main clock mode to the PLL clock mode or by reset Writing 1 to TBOF has no meaning 1 is read at reading TBOF by a read modify write family instruction bit 10 TBR TBR clears all bits of the time base timer counter to 0 Writing 0 to TBR clears the time base counter Wr...

Страница 231: ...this bit is 0 it indicates that the oscillation stabilization wait time is in progress The oscillation stabilization wait time is fixed to 2 14 cycles sub clock SCE is initialized to 0 at power on reset or at stop bit 5 WTIE WTIE enables interval interrupts by the watch timer When WTIE is 1 interrupts are enabled when it is 0 interrupts are disabled Resets initialize WTIE to 0 The WTIE bit can be ...

Страница 232: ...ven in Table 9 4 Resets initialize these bits to 000 These bits can be both read and written When writing these bits clear bit 4 WT0F concurrently Table 9 4 Selection of Watch Timer Interval WTC2 WTC1 WTC0 Interval Time 0 0 0 31 25 ms 0 0 1 62 5 ms 0 1 0 125 ms 0 1 1 250 s 1 0 0 0 50 s 1 0 1 1 00 s 1 1 0 2 00 s 1 1 1 4 00 s The interval time is the value when the sub clock is 32 768 kHz ...

Страница 233: ...termined time due to software nullfunction or hardware upset of program Time base timer The time base timer has the timer function for the oscillation stabilization time wait for the clock source of watchdog timer main clock and PLL clock It also has the interval interrupt function that generates interrupts at a certain cycle Watch timer The watch timer has the timer function for the oscillation s...

Страница 234: ...ng program execution To be more specific 0 must be written to the WTE bit of the WDTC register The watchdog counter is composed of the 2 bit counter using the carrying up signal of the time base timer as the clock source So when the time base timer is cleared the watchdog reset occurrence time may become longer than the setting Fig 9 5 Watchdog Timer Operation n Stop of watchdog timer The watchdog...

Страница 235: ...s cleared immediately before rising edge of count clock Maximum interval time When WTE bit is cleared immediately after rising edge of count clock Clock selector 2 divided circuit 2 divided circuit 2 bit counter Reset circuit Reset signal WTE Bit Enabling count output circuit Count enabled and cleared a b c d WTE bit cleared 7 count clock cycle 2 Watchdog reset generated Count clock a 2 divided va...

Страница 236: ...the TBC1 and 0 bits of the TBTC register The setting of this flag is determined based on the time when the time base timer was last cleared When a transition is performed from the main clock mode to the PLL clock mode the time base timer is cleared temporarily because it is used as the oscillation stabilization wait timer for PLL clock When a transition is performed to the stop mode the TBOF flag ...

Страница 237: ...lear until an overflow of the bit for the oscillation stabilization wait time However when restoring to the PLL clock mode from the time base timer mode the time base timer counter is not cleared so the oscillation stabilization wait time starts in the middle of the increment Table 9 6 shows the time base timer counter clear and the oscillation stabilization wait time Table 9 6 Time base Timer Cou...

Страница 238: ...ared by a power on reset a transitionto the stop mode and by writing 0 to the WTR bit of the WTC register The watchdog timer and the interval interrupt that use the output of the watch timer are affected by clearing the watch timer n Interval interrupt function of watch timer The interval interrupt function generates interrupts at a certain cycle the carrying up signal of the watch timer The WTOF ...

Страница 239: ...upt request Clear the TBOF of the time base timer control register when the TBIE bit or the interrupt level mask register ILM of the processor status PS masks the time base timer interrupt Influence of clearing time base timer Clearing the time base timer counter influences the following operations When using interval timer function interval interrupt of time base timer When using watchdog timer U...

Страница 240: ...oscillation stabilization wait time is counted using the time base timer Fig 9 7 Operation of Time base Timer Cleared by interrupt processing routine Sleep Sleep cancelled by interval interrupt Stop Counter value 3FFFFH Oscillation stabilization wait time overflow Cleared by transition to stop mode Counter cleared TBTC TBR 0 Power on reset option Interval cycle TBTC TBC1 TBC0 11H CPU operation sta...

Страница 241: ...val time of the watchdog timer Coding example WDTC EQU 0000A8H Watchdog timer control register WTE EQU WDTC 2 Watchdog control bit Main program CODE CSEG START Stack pointer SP already initialized WDG_START MOV WDTC 00000011B Watchdog timer started Interval time of 2 21 2 18 cycles selected Main loop MAIN CLRB I WTE Watchdog timer cleared 2 bits cleared periodically Processing by user JMP MAIN Wat...

Страница 242: ...ram CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupts disabled MOV I ICR12 00H Interrupt level 0 highest MOV I TBTC 10010000B Upper 3 bits fixed Interrupts enabled TBOF cleared Counter cleared Interval time of 212 HCLK selected MOV ILM 07H ILM in PS set to level 7 OR CCR 40H Interrupts enabled LOOP MOV A 00H Infinite loop MOV A 01H BRA LOOP Interrupt program WARI CLRB I ...

Страница 243: ... 3 Pins of 16 bit Reload Timer 10 7 10 4 Registers for 16 bit Reload Timer 10 8 10 5 Interrupt of 16 bit Reload Timer 10 15 10 6 Operation of 16 bit Reload Timer 10 16 10 7 Precautions at Using 16 bit Reload Timer 10 24 10 8 Program Example of 16 bit Reload Timer 10 25 10 16 BIT RELOAD TIMER ...

Страница 244: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 10 2 ...

Страница 245: ... reload timer is as shown in Table 10 1 Table 10 1 Operating Mode of 16 bit Reload Timer Clock Mode Counter Operation Operation of 16 bit Reload Timer Reload mode Internal clock mode One shot mode Software trigger operation External trigger operation External gate input operation Reload mode Event count mode external clock mode One shot mode Software trigger operation n Internal clock mode The cou...

Страница 246: ...es are values when the machine clock is 16 MHz One shot mode When decrementing causes an underflow 0000H FFFFH counting is stopped An underflow can generate an interrupt During counting a rectangular wave indicating that counting is in progress can be output from the TOT0 and TOT1 pins Remarks 1 The 16 bit reload timer can be used to generate the UART baud rate 2 The 16 bit reload timer can be use...

Страница 247: ...ister 16 bit timer register decrement counter UF TMRLR0 1 TMRLR1 TMR0 1 TMR1 Count clock generation circuit Prescaler Valid clock determination circuit Clear 3 Gate input CLK CLK Input controller Clock selector Pin Output signal generation circuit Pin Reload controller Operation controller Timer control status register TMCSR0 1 TMCSR1 3 2 Machine clock φ Function selection Select signal Reload sig...

Страница 248: ...ontrols the 16 bit reload timer start and stop 16 bit timer register TMR0 1L TMR0 1H The register is the 16 bit decrement counter At reading the current value is read 16 bit reload register TMRLR0 1L TMRLR0 1H The register sets the interval time of the 16 bit reload timer The setting value of this register is loaded into the 16 bit timer register to be decremented Timer control status register TMC...

Страница 249: ...s set to enabled TMCSR0L OUTE 1 P07 TIN1 Port 0 I O timer input Set to the input port DDR0 bit 7 0 P06 TOT1 Port 0 I O timer output CMOS Output CMOS hysteresis input Not provided Provided Timer output is set to enabled TMCSR1L OUTE 1 n Block diagram of pins of 16 bit reload timer Figure 10 2 shows the block diagram of the pins of 16 bit reload timer Fig 10 2 Block Diagram of Pins of 16 bit Reload ...

Страница 250: ... 10 3 Registers for 16 bit Reload Timer The register functions as a 16 bit timer register TMCR0 1 at reading and as a 16 bit reload register TMCRLR0 1 at writing TMCSR0 timer control status register TMR0 TMRLR0 16 bit timer register 16 bit reload register bit 15 bit 8 bit 7 bit 0 16 bit reload timer 0 Address 000051H 50H 000053H 52H 000055H 54H 000057H 56H TMCSR1 timer control status register TMR1...

Страница 251: ...z Operation Mode Select Bit in internal clock mode MOD2 MOD1 MOD0 Function of Input Pin Effective Edge Level 0 0 0 Trigger disabled 0 0 1 Rising edge 0 1 0 Falling edge 0 1 1 Trigger input Both edges 1 X 0 L level 1 X 1 Gate input H level Operation Mode Select Bit in event count mode MOD2 MOD1 MOD0 Function of Input Pin Effective Edge X 0 0 X 0 1 Rising edge X 1 0 Falling edge X 1 1 Trigger input ...

Страница 252: ... 9 bit 8 bit 7 MOD2 MOD1 MOD0 Operating mode select bits In internal clock mode The MOD2 bit selects the function of the input pin When the MOD2 bit is 0 the input pin serves as the trigger input pin When an effective edge is input the value of the reload register is loaded into the counter to continue counting MOD1 and 0 bits select the type of the effective edge When the MOD2 bit is 1 the input ...

Страница 253: ...ow occurs When 1 is written to this bit operation not affected INTE Interrupt Request Enable Bit 0 Interrupt request output disabled 1 Interrupt request output enabled RELD Reload Select Bit 0 One shot mode 1 Reload mode Pin Output Level Select Bit OUTL In One shot Mode RELD 0 In Reload Mode RELD 1 0 H rectangular wave output during counting L toggle wave output at starting counting 1 L rectangula...

Страница 254: ... concurrently with the underflow to continue counting When this bit is 0 the one shot mode is enabled and an underflow stops counting bit 3 INTE Interrupt request enable bit This bit enables and disables the interrupt request output to the CPU When this bit and the interrupt request flag bit UF are 1 an interrupt request is output bit 2 UF Underflow interrupt request flag bit This bit is set to 1 ...

Страница 255: ...lue of the TMR register is held Notes 1 The TMR register can also be read during counting but always use a word transfer instruction such as MOVW A 003AH 2 The 16 bit timer register TMR0 1 is a read only register but it is allocated to the same address as the write only 16 bit reload register TMRLR0 1L TMRLR0 1H Consequently when a write is performed the value of TMR is not affected but the write ...

Страница 256: ...e value set in the 16 bit reload register TMRLR0 1L TMRLR0 1H is reloaded into the counter by an underflow to continue decrementing In the one shot mode the counter stops at FFFFH by an underflow Notes 1 Write to this register with the counter stopped TMCSR0 1 CNTE 0 Also write to with the word transfer instruction MOVW 003AH A 2 The 16 bit reload register TMRLR0 1L TMRLR0 1H is a write only regis...

Страница 257: ...CSR0 1 INTE 1 interrupt request is output to the interrupt controller n 16 bit reload timer interrupt and EI 2 OS Table 10 8 shows the 16 bit reload timer interrupt and the EI 2 OS Table 10 8 16 bit Reload Timer Interrupt and EI 2 OS Interrupt Control Register Address of Vector Table Channel Interrupt No Register Name Address Lower Upper Bank EI 2 OS 16 bit reload timer 0 17 11H ICR03 0000B3H FFFF...

Страница 258: ...16 bit reload timer as the event counter the following setting is required Fig 10 9 Setting of Event Counter Mode bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TMCSR CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 Except for 11 TMRLR Initial value of counter reload value set Used bit 1 1 set bit 15 bit 14 bit 13 bit 12 bit 11 bit 1...

Страница 259: ... pin initial value output Counter value at stop state retained undefined from immediately after a reset to loading RUN state TIN pin functions as TIN pin TOT pin functions as TOT pin Counter running CNTE 1 TRG 0 CNTE 0 CNTE 0 UF 1 RELD 0 One shot mode UF 1 RELD 1 Reload mode LOAD Loading value of reload register to counter TRG 1 software trigger TRG 1 software trigger External trigger from TIN Loa...

Страница 260: ... with the counter enabled When the value of the counter underflows 0000H FFFFH the value of the 16 bit reload register TMRLR0 1L TMRLR0 1H is loaded into the counter and the count continues At this point the underflow interrupt request flag bit UF is set to 1 and when the interrupt request enable bit INTE is 1 an interrupt request is issued Also a toggle wave that is inverted for each underflow ca...

Страница 261: ...10 13 shows the gate input operation in the reload mode Fig 10 13 Count Operation in Reload Mode Operation of Software Trigger and Gate Input Note The width of the gate pulse input to the TIN0 1 pin must be 2 φ or more Count clock Counter Data load signal UF bit CNTE bit TIN pin TOT pin Reload data 2T to 2 5T T Machine cycle It takes 2 T to 2 5 T time from inputting the external trigger to loading...

Страница 262: ...he counter enabled When the value of the counter underflows 0000H FFFFH the counter is stopped with the state of FFFFH At this point the underflow interrupt request flag bit UF is set to 1 and when the interrupt request enable bit INTE is 1 an interrupt request is issued Also a rectangular wave which indicates counting is in progress can be output from the TOT pin Operation of software trigger The...

Страница 263: ...gure 10 16 shows the gate input operation in the one shot mode Fig 10 16 Count Operation in One shot Mode Operation of Software Gate Input Note The width of the gate pulse input to the TIN pin must be 2 φ or more Count clock Counter Data load signal UF Bit CNTE Bit TIN Pin TO Pin Reload data 2T to 2 5T T Machine cycle It takes 2 T to 2 5 T time from inputting the external trigger to loading the re...

Страница 264: ...are set to 1 concurrently the count is started at the same time as the count enabling Operation in reload mode When the counter value underflows 0000H FFFFH the value of the 16 bit reload register TMRLR0 1L TMRLR0 1H is loaded into the counter and the count continues An interrupt request is issued at this point when the underflow interrupt request flag bit UF is 1 and the interrupt request enable ...

Страница 265: ...at the count is in progress can be output from the TOT0 1 pin Figure 10 18 shows the count operation in the one shot mode Fig 10 18 Count Operation in One shot Mode Operation of Event Count Mode Note The width of the H or L of clock input to the TIN0 1 pin must be 4 φ or more TIN pin Counter Data load signal UF bit CNTE bit TRG bit TO pin Reload data T T Machine cycle It takes 1 T time from inputt...

Страница 266: ...the CSL1 and CSL0 bits of the timer control status register TMCSR0 1L TMCSR0 1H when the counter is stopped TMCSR0 1 CNTE 0 Precautions for interrupt No return can be performed from interrupt handling when the UF bit of the timer control status register TMCSR0 1L TMCSR0 1H is 1 and the interrupt request is already enabled TMCSR0 1 INTE 1 To return from interrupt handling always clear the UF bit Si...

Страница 267: ...uest flag bit CNTE EQU TMCSR 1 Counter operation enable bit TRG EQU TMCSR 0 Software trigger bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupts disabled MOV I ICR03 00H Interrupt level 0 highest CLRB I CNTE Counter suspended MOVW I TMRLR 30D4H Data set for timer generating interrupt at 25 ms intervals MOVW I TMCSR 00001000000011011B Operation of interval ...

Страница 268: ...1 Counter operation enable bit TRG EQU TMCSR 0 Software trigger bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupts disabled MOV I ICR09 00H Interrupt level 0 highest MOV I DDR1 00H Set P12 TIN0 pin to input CLRB I CNTE Counter suspended MOVW I TMRLR 2710H Set reload value to 10000 times MOVW I TMCSR 0000110010001011B Counter operation external trigger ris...

Страница 269: ...11 1 Overview of Input Capture 11 3 11 2 Block Diagram of Input Capture 11 4 11 3 List of Input Capture Registers 11 5 11 4 Explanation of Operation 11 13 11 INPUT CAPTURE ...

Страница 270: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 11 2 ...

Страница 271: ... selected Rising falling and both edges Four input captures can be operated independently An interrupt can be generated at the effective edge of the external input signal 16 bit free run timer 1 The 16 bit free run timer is composed of a 16 bit up counter control register 16 bit comapare clear register and prescaler The output value of this counter is used as the base time base timer of the input ...

Страница 272: ...am Fig 11 1 Block Diagram F 2 MC 16LX Bus IVF IVFE STOPMODE SCLRCLK2 CLK1 CLK0 Divider 16 bit free run timer Interrupt 31 1FH φ 16 bit compare clear register Compare circuit MSI3 to 0 ICLR ICRE Interrupt 33 21H Edge detection EG01 EG00 EG11 EG10 A D start Clock Edge detection ICE0 ICE1 ICP0 ICP1 Capture data register 0 2 Capture data register 1 3 Interrupt 19 23 15 21 IN0 2 IN1 3 ...

Страница 273: ...a register upper bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Address 000027H T15 T14 T13 T12 T11 T10 T09 T08 TCDT R W R W R W R W R W R W R W R W Read write 0 0 0 0 0 0 0 0 Initial value Timer data register lower bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address 000026H T07 T06 T05 T04 T03 T02 T01 T00 TCDT R W R W R W R W R W R W R W R W Read write 0 0 0 0 0 0 0 0 Initial value Tim...

Страница 274: ... R R R R R R R R Read write X X X X X X X X Initial value Capture control register upper bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address 00006AH ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 ICS23 R W R W R W R W R W R W R W R W Read write 0 0 0 0 0 0 0 0 Initial value Capture control register lower bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address 000068H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG0...

Страница 275: ...n 0 Effective edge not detected Initial value 1 Effective edge detected ICPn Number of n corresponds to the channel number of input capture Input capture data register upper bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 IPCP0 to 3 R R R R R R R R Read write X X X X X X X X Initial value Input capture data register lower bit 7 bit 6 bit 5 bit 4 bit 3 ...

Страница 276: ... value 1 Interrupt enabled ICEn Number of n corresponds to the channel number of input capture bits 3 to 0 EG31 30 EG21 20 EG11 10 EG01 00 These bits specify the polarity of the effective edge of the external input and also enable the input capture operation EG31 EG30 Polarity of Edge Detection 0 0 Edge not detected stop state Initial value 0 1 Rising edge detected 1 0 Falling edge detected 1 1 Bo...

Страница 277: ...ation Perform word access to this register When this register value and the 16 bit free running timer value match the the latter is initialized to 0000 and the compare clear interrupt flag is set Also an interrupt request is issued to the CPU when interrupts are enabled Timer data register upper bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Address 000027H T15 T14 T13 T12 T11 T10 T09 T08 T...

Страница 278: ...d the interrupt handling is performed at third times 010B is set However when 000B is set the interrupt factor is not masked bit 9 ICLR This bit is the compare clear interrupt request flag This bit is set to 1 when the value of the compare clear register and the value of the 16 bit free run timer match and the counter is cleared An interrupt is generated when the interrupt request enable bit bit 8...

Страница 279: ...g disabled stop Note When the 16 bit free run timer stops the output compare operation also stops bit 4 MODE This bit sets the initialization condition of the 16 bit free run timer When this bit is 0 the counter value can be initialized by reset and the clear bit bit 3 CLR When this bit is 1 the counter value can be initialized by reset the clear bit bit 3 CLR and a match with the value of the com...

Страница 280: ...so a performed when the output compare and input capture are in the stop state CLK2 CLK1 CLK0 Count Clock φ φ 16 MHz φ φ 8 MHz φ φ 4 MHz φ φ 1 MHz 0 0 0 φ 62 5 ns 125 ns 0 25 µs 1 µs 0 0 1 φ 2 125 ns 0 25 µs 0 5 µs 2 µs 0 1 0 φ 4 0 25 µs 0 5 µs 1 µs 4 µs 0 1 1 φ 8 0 5 µs 1 µs 2 µs 8 µs 1 0 0 φ 16 1 µs 2 µs 4 µs 16 µs 1 0 1 φ 32 2 µs 4 µs 8 µs 32 µs 1 1 0 φ 64 4 µs 8 µs 16 µs 64 µs 1 1 1 φ 128 8 µs...

Страница 281: ...reset is canceled the 16 bit free run timer starts counting at 0000 This counter value works as the base time of the 16 bit output compare and 16 bit input capture 16 bit input capture When the set effective edge is detected the 16 bit input capture can write the value of the 16 bit free run timer to the capture register to generate an interrupt ...

Страница 282: ...iming of 16 bit input capture Fig 11 3 Capture Timing for Input Signal Interrupt again by effective edge Time Counter value BFFFH Undefined 3FFFH 7FFFH BFFFH Interrupt by software Undefined Undefined FFFFH BFFFH 7FFFH 3FFFH 0000H Reset IN0 IN1 Example of IN Data register 0 Data register 1 Example of data register Capture 0 interrupt Capture 1 interrupt Example of capture interrupt Capture 0 rising...

Страница 283: ...quired When 1 is written to the SCLR bit of the TCCS register during operation When 0000H is written to the TCDT register while timer stops An interrupt can be generated when an overflow occurs and the counter is cleared at a compare match with the value of compare clear register a compare match interrupt needs mode seting Fig 11 4 Clearing Counter by Overflow Fig 11 5 Clearing Counter when Value ...

Страница 284: ... The counter clear matched with a compare clear register is performed synchronously with count timing Fig 11 6 Clearing Timing of 16 bit Free run Timer n Counting timing of 16 bit free run timer The 16 bit free run timer is incremented by input clock internal or external clock It is incremented by rising edge at selecting the external clock Fig 11 7 Count Timing of 16 bit Free run Timer φ Value of...

Страница 285: ...guration of UART 12 5 12 3 Pin of UART 12 8 12 4 Registers for UART 12 9 12 5 Interrupt of UART 12 18 12 6 Baud Rate of UART 12 22 12 7 Operation of UART 12 28 12 8 Precautions at Using UART 12 38 12 9 Program Example of UART 12 39 12 UART ...

Страница 286: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 12 2 ...

Страница 287: ...tart bit stop bit Asynchronous start stop synchronization to clock Baud rate Dedicated baud rate generator The baud rate can be selected from among eight types Any baud rate can be set by external clock Internal clock An internal clock supplied from the 16 bit reload timer can be used Data length 7 bits for asynchronous normal mode only 8 bits Signal type NRZ Non Return to Zero type Detection of r...

Страница 288: ...ed as the stop bit n Interrupt related to UART and EI2 OS Table 12 3 Interrupt Related to UART and EI2 OS Interrupt Control Register Vector Table Address Interrupt Factor Interrupt No Register Name Address Lower Upper Bank EI 2 OS UART1 receive interrupt 37 25H ICR13 0000BDH FFFF68H FFFF69H FFFF6AH UART1 transmit interrupt 38 26H ICR13 0000BDH FFFF64H FFFF65H FFFF66H UART0 receive interrupt 39 27H...

Страница 289: ...ng 11 blocks Clock selector Receive controller Transmit controller Reception state determining circuit Receive shift register Transmit shift register Mode register SMR0 1 Control register SCR0 1 Status register SSR0 1 Input data register SIDR0 1 Output data register SODR0 1 ...

Страница 290: ...OS to CPU SMR0 SMR1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE Control bus Receive parity counter Receive bit counter Start bit detection circuit Transmit start circuit Transmit bit counter Transmit parity counter Transmit interrupt signals 40 28H 38 26H Receive shift register Termination of reception SIDR0 SIDR1 Transmit shift register SODR0 SODR1 Pin Pin Reception state determining circuit Internal d...

Страница 291: ... when parity is provided Receive shift register The receive shift register writes the receive data input from the SIN0 pin while shifting bit by bit and when the data reception is completed transfers the receive data to the SIDR register Transmit shift register Data written to SODR is transferred to the transmit shift register and then the data is output to the SOT0 pin while shifting bit by bit M...

Страница 292: ...rt0 I O serial data output Set to output enabled SMR SOE 1 Set to the input port at clock input DDR0 bit 2 0 DD0 bit 5 0 P02 SCK0 P05 SCK1 Port0 I O serial clock I O CMOS output CMOS hysteresis input Not provided Provided Set to output enabled at clock output SMR SCKE 1 n Block diagram of pins of UART Fig 12 2 Block Diagram of Pins of UART Internal data bus PDR port data register PDR read PDR writ...

Страница 293: ...s Fig 12 3 List of UART Registers SMR mode register CH0 000035H 34H CH1 000039H 38H CH0 000037H 36H CH1 00003BH 3AH CH0 00003DH CH1 00003FH SIDR SODR input output data register Unused SCR control register SSR status register bit 15 bit 8 bit 7 bit 0 CDCR communication prescaler control register Address ...

Страница 294: ...bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 R W R W R W R W R W W R W R W 00000100B Initial value TXE Transmit Enable Bit 0 Disables transmitting 1 Enables transmitting RXE Receive Enable Bit 0 Disables receiving 1 Enables receiving REC Receive Error Flag Clear Bit 0 Clears FRE ORE and PE flags 1 Does not change this bit and has no affect on others A D Address Data Select Bit 0 Data frame ...

Страница 295: ...ata format for frame sent received in multiprocessor mode mode 1 Normal data is selected when this bit is 0 Address data is selected when it is 1 bit 10 REC Receive error flag clear bit Bit to clear FRE ORE and PE flags of status register SSR These flags are cleared when 0 is written to this bit When 1 is written this bit remains unchanged and has no affect on others Note When the receive interrup...

Страница 296: ...al value SOE Serial data Output enable Bit P37 SOT0 pin P61 SOT1 pin 0 Serves as general purpose I O port 1 Serves as serial data output pin of UART0 1 SCKE Serial Clock Output enable Bit P40 SCK0 pin P62 SCK1 pin 0 Serves as general purpose I O port or as clock input pin of UART0 1 1 Serves as clock output pin of UART0 1 CS2 to CS0 Clock Select Bit 000B to 101B Baud rate by dedicated baud rate ge...

Страница 297: ...CKE Serial clock output enable bit Bit to control serial clock I O When this bit is 0 the P02 SCK0 pin serves as the general purpose I O port P02 or the serial clock input pin When this bit is 1 the P02 SCK0 pin serves as the serial clock output pin Notes When using the P02 SCK0 pin as the serial clock input SCKE 0 set P02 to the input port Also select the external clock by the clock select bits S...

Страница 298: ...request output 1 Enables transmit interrupt request output RIE Receive Interrupt Request Enable Bit 0 Disables receive interrupt request output 1 Enables receive interrupt request output BDS Transfer Direction Select Bit 0 LSB first transfer starts at least significant bit 1 MSB first transfer starts at most significant bit TDRE Transmit Data Empty Flag Bit 0 With transmit data writing of transmit...

Страница 299: ...red to 0 When this bit and the RIE bit are 1 a receive interrupt request is output bit 11 TDRE Transmit data empty flag bit This bit is the flag indicating the state of the output data register SODR When transmit data is written to SODR this bit is cleared to 0 When data is loaded into the transmit shift register and transmission starts this bit is set to 1 When this bit and the TIE bit are 1 a tr...

Страница 300: ...utput data register Fig 12 8 Output Data Register SODR0 1 When transmit data is written to this register when transmission is enabled transmit data is transferred to the transmission shift register converted to serial data and output from the serial data output pin SOT0 pin When the data length is 7 bits the upper 1 bit D7 is invalid data When transmit data is written to this register the transmit...

Страница 301: ...own below bit 15 MD Machine clock Divide mode select This bit is the operation enable bit for the communication prescaler 0 The communication prescaler stops 1 The communication prescaler operates bits 11 to 8 DIV3 to DIV0 DIVide 3 to 0 The clock division ratio of the machine clock is determined according to Table 12 8 Table 12 8 Communication Prescaler MD DIV3 DIV2 DIV1 DIV0 div 0 Stop 1 0 0 0 0 ...

Страница 302: ...ng 0 to receive error flag clear bit SSR1 REC Trans mission TDRE Transmit buffer SODR vacant SSR0 1 TIE Writing transmit data Used bit Unused bit Receive interrupt In the receive mode the corresponding flag bit of the status register is set to 1 when data receive completed SSR0 1 RDRF an overrun error SSR0 1 ORE a framing error SSR0 1 FRE or a parity error SSR0 1 PE When any one of these flag bits...

Страница 303: ...0 28H ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH Function provided for stopping EI2 OS by detecting receive error in UART EI2 OS can be used when interrupt factors sharing ICR13 ICR14 or interrupt vector are not used n EI2 OS function of UART The UART has a circuit with to conforms to EI 2 OS Consequently EI 2 OS can be started separately for receive interrupts and transmit interrupts At reception EI 2...

Страница 304: ...et Operation mode 1 asynchronous multiprocessor mode When RDRF is set to 1 at detection of the stop bit and a receive error is already occurred at this point the error flag ORE FRE is set No parity error can be detected Operation mode 2 synchronous normal mode When RDRF is set to 1 at detection of the end bit D7 of receive data and a receive error is already occurred at this point the error flag O...

Страница 305: ...ion Immediately after the TDRF flag is set to 1 when the transmit interrupt is enabled SSR0 1 TIE 1 a transmit interrupt request 38 40 is issued Note Since the TDRE is 1 in the initial state when the transmit interrupt is enabled TIE 1 a transmit completion interrupt is generated immediately The TDRE is a read only bit and can only be cleared when new data is written to the output data register SO...

Страница 306: ...generator and can select one from the eight types of baud rate by the mode register SMR0 1 The UART selects an asynchronous baud rate or clock synchronous baud rate by the frequency of the machine clock and the BCH and CS2 to CS0 of the mode register SMR0 1 Baud rate by internal timer The internal clock supplied from the 16 bit reload timer is used as a baud rate as is synchronous or is used after...

Страница 307: ...ynchronous The internal fixed division ratio is selected Clock selector When 000B to 101B 1 1 synchronous 1 16 asynchronous When 110B 1 1 synchronous 1 16 asynchronous When 111B 4 Machine clock division ratio Prescaler φ Decrement counter UF Clock selector φ φ 21 φ 23 φ 25 Prescaler TMCSR0 1 CSL1 CSL0 2 16 bit reload timer 0 Pin Baud rate SMR0 1 MD1 selection of clock synchronous asynchronous mode...

Страница 308: ...ock division ratio asynchronous transfer clock division ratio Synchronous baud rate φ prescaler clock division ratio synchronous transfer clock division ratio φ Machine clock frequency Division ratio of prescaler common to asynchronous and synchronous modes The division ratio of the machine clock is specified by the DIV3 to DIV0 bits of the CDCR0 1 as shown in Table 12 11 Table 12 11 Selection of ...

Страница 309: ...ting CS2 to CS0 to 110 the baud rate is obtained using the following expressions when using the reload timer Asynchronous start stop synchronization φ N 16 2 n 1 CLK synchronous φ N 2 n 1 N count clock source of timer n timer reload value of timer Note In mode 2 CLK synchronous mode SCK0 is delayed for three clocks maximum against SCK1 Theoretically the transfer rate that can be implemented is 1 3...

Страница 310: ...ne clock 7 3728 MHz Table 12 14 Baud Rate and Reload Value Reload Value Clock Asynchronous start stop synchronization Clock Synchronous Baud Rate X 2 1 machine cycle 2 divided X 23 machine cycle 8 divided X 2 1 machine cycle 2 divided X 2 3 machine cycle 8 divided 38400 2 47 11 19200 5 95 23 9600 11 2 191 47 4800 23 5 383 95 2400 47 11 767 191 1200 95 23 1535 383 600 191 47 3071 767 300 383 95 614...

Страница 311: ...o the SCKE bit of the mode register SMR0 1 to make the pin serve as an external clock input pin As shown in Figure 12 13 the baud rate is selected based on the external clock input from the SCK0 pin Since the internal division ratio is fixed the cycle of the external input clock must be changed to change the baud rate Fig 12 13 Baud Rate Selector by External Clock Expressions to obtain baud rate A...

Страница 312: ... the data length parity synchronous or asynchronous mode etc must be the same for all CPUs The operation modes are selected as follows For the 1 to 1 connection the same operation mode either operation mode 0 or 2 must be used for the two CPUs For the asynchronous mode select operation mode 0 for the synchronous mode select operation mode 2 For the master slave mode connection operation mode 1 is ...

Страница 313: ...mit data is able to be set When the transmit interrupt request is already enabled SSR0 1 TIE 1 at this point the transmit interrupt request is output to request the transmit data to be set in SODR0 1 When the transmit data is written to SODR0 1 the TDRE flag is cleared to 0 Reception When the reception is enabled SCR0 1 RXE 1 reception is being performed When the start bit is detected one frame da...

Страница 314: ...f the control register SCR0 1 and even or odd parity is set by the P bit No parity can be used in operation mode 1 asynchronous multiprocessor mode and operation mode 2 synchronous normal mode Figure 12 15 shows transmission reception when parity is enabled Fig 12 15 Transmit Data when Parity Enabled ST Start bit SP Stop bit Note Parity cannot be used in operation modes 1 and 2 SIN0 1 ST 1 0 1 1 0...

Страница 315: ...ata is transmitted the synchronous clock for data reception is generated automatically When the external clock is already selected the clock for exactly one byte must be supplied from outside after ensuring that data is present SSR0 1 TDRE 0 in the output data register SODR0 1 of the transmit UART Also before and after transmitting always set the mark level to the H level Error detection Only over...

Страница 316: ...rupt not used TIE 1 When interrupt used 0 When interrupt not used Starting communications Communications are started by writing data to the output data register SODR0 1 Note that even when starting communications to receive data always write temporary data to SODR Terminating communications When transmission reception of one data frame is terminated the RDRF flag of the status register SSR0 1 is s...

Страница 317: ...17 Setting of Operation Mode 0 for UART1 Inter CPU connection Connect the two CPUs as shown in Figure 12 18 Fig 12 18 Example of Bidirectional Communication Connection for UART1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCR1 SMR1 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 SCKE SOE Mode 0 0 0 0 Mode 2 0 1 0 1 0 SSR1 SIDR1 SODR1 PE ORE...

Страница 318: ...ry byte in this example Figure 12 19 shows an example of the bidirectional communication flow Fig 12 19 Example of Bidirectional Communication Flow Transmit side Start Set the operation mode 0 or 2 Set the 1 byte data in SODR to communicate Read and process receive data Receive data exist NO Read and process receive data YES Transmit 1 byte data Data transmission ANS Receive side Start Set the ope...

Страница 319: ... system is composed by connecting the master CPU and plural slave CPUs to two common communications lines UART1 can only be used as the master CPU Fig 12 21 Example of Master Slave Mode Communication Connection for UART bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCR1 SMR1 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 SCKE SOE 0 1 0 0 1 0...

Страница 320: ...dress transmission reception A D 1 8 bit address Data transmission reception Mode 1 A D 0 8 bit data Not provided Asynchronous 1 bit or 2 bits Communication procedure Communications start when the master CPU transmits the address data The address data which A D bit is 1 selects the slave CPU which is a communication destination Each slave CPU determines the address data by the program and when the...

Страница 321: ...t the SIN pin to serial data input Set 1 byte data address data that selects the slave CPU to D0 to D7 to transmit A D 1 Set 0 to A D Reception enabled Communicate with slave CPU Communication terminated YES NO Communicate with the other slave CPU YES NO Reception disabled Master CPU Start END ...

Страница 322: ...ion mode when data transfer is stopped If the communications mode is set during data transmission reception those data are not assured Synchronous mode The clock synchronous mode operation mode 2 of the UART uses the clock control I O ecpansion serial mode the start and stop bits are not affixed to the data Timing of transmit interrupt enable Since the default initial value of the transmit data em...

Страница 323: ... register SMR EQU 000034H Mode register SCR EQU 000035H Control register SIDR EQU 000036H Input data register SODR EQU 000036H Output data register SSR EQU 000037H Status register REC EQU SCR 2 Receive error flag clear bit Main program CODE CSEG ABS OFFH START Stack pointer SP already initialized AND CCR 0BFH Interrupt disabled MOV I ICR14 00H Interrupt level 0 highest MOV I DDR0 00000000B Set SIN...

Страница 324: ...WARI MOV A SIDR Receive data read CLRB I REC Receive interrupt request flag cleared Processing by user RETI Return from interrupt CODE ENDS Vecter setting VECT CSEG ABS 0FFH ORG 0FF60H Set vector to interrupt 39 27H DSL WARI ORG 0FFDCH Reset vector set DSL START DB 00H Set to single chip mode VECT ENDS ...

Страница 325: ...13 1 Overview of PPG Timer 13 3 13 2 Block Diagram of PPG Timer 13 4 13 3 Registers for PPG Timer 13 5 13 4 Operation of PPG Timer 13 10 13 PPG TIMER ...

Страница 326: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 13 2 ...

Страница 327: ...a D A converter by an external circuit One shot function It is possible to detect the edge of the trigger input and output a single pulse Pin control When a duty match occurs the pin is set to 1 this is preferred When a borrow occurs in the counter the pin is reset to 0 In the fixed output value mode all L or all H can be output easily The polarity can be specified 16 bit decrement counter The cou...

Страница 328: ... diagram of PPG timer is given below n Block diagram Fig 13 1 Block Diagram of PPG Timer Machine clock Load PCNT 16 bit decrement counter Start Borrow 1 1 1 4 1 5 1 16 1 32 PCSR PDUT Edge detection P05 TRG Software trigger S Q R Interrupt selection Interrupt Invert bit PPG output PPG Mask CMP Enable Trigger input Prescaler ...

Страница 329: ...control status register lower Address ch0 00002AH Address ch1 00002CH Address ch2 00002EH PCNTH0 to 2 Read write Initial value Read write Initial value PCNTL0 to 2 Address ch0 003921H Address ch1 003929H Address ch2 003931H DC15 Read write Initial value PDCRH0 to 2 Address ch0 003920H Address ch1 003928H Address ch2 003930H Read write Initial value PDCRL0 to 2 Address ch0 003923H Address ch1 00392...

Страница 330: ...M operation that issues a pulse continuously or the one shot operation that issues a single pulse It cannot be rewritten during operation 0 PWM operation initial value 1 One shot operation bit 12 RTRG Restart enable bit This bit enables restart by the software trigger It cannot be rewritten during operation 0 Disables restart initial value 1 Enables restart CNTE STGR MDSE RTRG CKS1 CKS0 PGMS bit 1...

Страница 331: ...ed bit Always write 0 to this bit bits 7 6 EGS1 EGS0 Trigger input edge select bits Whichever mode is selected the software trigger is enabled when 1 is written to the software trigger bit EGS1 EGS0 Edge Selection 0 0 Invalid initial value 0 1 Rising edge 1 0 Falling edge 1 1 Both edges bit 5 IREN Interrupt request enable bit This is the interrupt enable bit for the PPG timer When this bit is 1 an...

Страница 332: ...ity PPG or invert polarity PPG bit 1 POEN PPG output enable bit When this bit is set to 1 PPG output is output from the pin 0 General purpose port initial value 1 PPG output pin bit 0 OSEL PPG output polarity specification bit This bit sets the polarity of the PPG output 0 Normal polarity initial value 1 Invert polarity The combinations of this bit and bit 9 PGMS are shown below PGMS OSEL PPG Outp...

Страница 333: ...05 CS04 CS03 CS02 CS01 CS00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W W W W W W W W X X X X x X X X Read write Initial value PCSRH0 to 2 Address ch0 003923H Address ch1 00392BH Address ch2 003933H Address ch0 003922H Address ch1 00392AH Address ch2 003932H Read write Initial value PCSRL0 to 2 PPG cycle setting register lower DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08 bit 15 bit 14 bit 13 bit ...

Страница 334: ...e of the output pulse is controlled by changing the PCSR value and the duty ratio is controlled by changing the PDUT value n When restart disabled Fig 13 2 Timing of Disabling PWM Operation Restart n When restart enabled Fig 13 3 Timing of Enabling PWM Operation Restart Trigger ignored Start trigger m n O PPG Rising edge detected 1 T n 1 µs T Count clock cycle 2 T m 1 µs m PCSR value n PDUT value ...

Страница 335: ...lter for the external TRG input add a filter if necessary 13 4 2 One shot Operation At one shot operation a single pulse of any width can be output by a trigger With restart enabled the counter is reloaded when the start trigger is detected during operation n When restart disabled Fig 13 4 Timing of Disabling One shot Operation Restart n When restart enabled Fig 13 5 Timing of Enabling One shot Op...

Страница 336: ...ll Hs for PWM output Software trigger Compare match Borrow Start trigger Load Clock Count value PPG Interrupt 0002h 0003h 0001h 0000h 0003h XXXX 2 5T max When a compare match causes an interrupt the same value as the cycle setting register is written to the duty setting register PPG Duty value incresed When a borrow causes an interrupt 1 is written to the PGMS mask bit Also when 0 is written to th...

Страница 337: ...nfiguration of LCD Controller Driver 14 4 14 3 LCD Controller Driver Pins 14 10 14 4 LCD Controller Driver Registers 14 12 14 5 LCD Controller Driver Display RAM 14 16 14 6 Explanation of Operation of LCD Controller Driver 14 18 14 LCD CONTROLLER DRIVER ...

Страница 338: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 14 2 ...

Страница 339: ...AM on the LCD panel using segment outputs and common outputs LCD driving voltage split resistors are contained Also external split resistors can be connected Up to 4 common outputs COM0 to COM3 and 24 segment outputs SEG0 to SEG23 can be used A 16 byte display data memory display RAM is contained Three different duties can be selected 1 2 1 3 and 1 4 limited by bias setting The LCD can be driven d...

Страница 340: ...drives the LCD LCDC control register LCRL LCRH Display RAM Prescaler Timing controller AC generator Common driver Segment driver Split resistors Block diagram for LCD controller driver Fig 14 1 Block Diagram for LCD Controller Driver 4 24 LCDC control register L LCRL Timing controller Prescaler Display RAM 16 8 bits LCDC control register H LCRH Split resistors Common driver Segment driver AC gener...

Страница 341: ...nerates the frame frequency by setting selected from four different frequencies Timing controller The timing controller controls common signals and segment signals based on the frame frequency and the LCRL register AC generator This circuit generates LCD driving AC waveform from the timing controller signals Common driver This is the driver for LCD common pins Segment driver This is the driver for...

Страница 342: ... power pins V0 to V3 Internal or external split resistors are selected using the LCDC control register driving power control bit LCRL VSEL When the VSEL bit is set to 1 the internal split resistors have current Consequently when using the internal split resistors set the VSEL bit to 1 and do not connect external split resistors Enabling of the LCD controller is inactive when the LCD operation stop...

Страница 343: ...it resistors used When the brightness does not increase by using internal split resistors connect an external VR variable resistor between Vcc and V3 and adjust the voltage of the V3 pin Fig 14 4 Brightness Adjustment when Internal Split Resistors Used R R R Q1 LCD controller enabled 1 2 bias V3 V2 V1 V0 V0 to V3 Voltages of V0 to V3 pins V2 V1 V0 Short circuited R R R Q1 1 3 bias V3 V2 V1 V0 V2 V...

Страница 344: ...or LCD controller driver External split resistor can be used by connection to the LCD driving power pins V0 to V3 Figure 14 5 and Table 14 2 shows the external split resistor connection and LCD driving voltage for each bias type Fig 14 5 External Split Resistor Connection Example Table 14 2 LCD Driving Voltage Setting V3 V2 V1 V0 1 2 bias VLCD 1 2VLCD 1 2VLCD VSS 1 3 bias VLCD 2 3VLCD 1 3VLCD VSS ...

Страница 345: ...esistors 0 must be written to the LCDC control register driving power control bit LCRL VSEL to isolate all the internal split resistors When all the internal split resistors are isolated when a value other than 00B is written to the LCDC control register display mode select bits LCRL MS1 MS0 the LCDC enable transistor Q1 is set to ON and current passes through the external split resistors When 00B...

Страница 346: ...pins V0 to V3 COM0 to COM3 pins The COM0 to COM3 pins are LCD common output pins SEG00 to SEG11 P36 SEG12 to P37 SEG13 P40 SEG14 to P47 SEG21 P90 SEG22 to P91 SEG23 pins The SEG00 to SEG11 pins are LCD segment output pins The P36 SEG12 to P37 SEG13 P40 SEG14 to P47 SEG21 and P90 SEG22 to P91 SEG23 pins can serve both as general purpose I O ports P36 to P37 P40 to P47 and P90 to P91 and as LCD segm...

Страница 347: ...egister PDR Port data register Stop mode SPL 1 or LCD enabling Pin Stop mode SPL 1 or LCD enabling Pch Nch SPL Pin state specification bit of standby control register STBC V0 to V3 Voltages of V0 to V3 pins Pch Nch Pch Nch Common segment control signal LCRH Setting P36 SEG12 to P37 SEG13 P40 SEG14 to P47 SEG21 P90 SEG22 to P91 SEG23 Internal data bus LCD driving voltage V3 or V2 Reset operation st...

Страница 348: ... Related to LCD Controller Driver CSS LCEN VSEL BK MS1 MS0 FP1 FP0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R W R W R W R W R W R W R W R W LCRL LCDC control register lower SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R W R W R W R W R W R W Address 006CH LCRH LCDC control register higher Address 006DH Initial value 00010000B Initial value X00X0000B R ...

Страница 349: ...alue FP1 FP0 Frame Cycle Select Bits 0 0 FC 213 N 0 1 FC 214 N 1 0 FC 215 N 1 1 FC 216 N N Time division count Fc Original oscillation MS1 MS0 Display Mode Select Bits 0 0 Stops LCD operation 0 1 1 2 duty output mode time division count N 2 1 0 1 3 duty output mode time division count N 3 1 1 1 4 duty output mode time division count N 4 BK Display Display Blanking Select Bit 0 Display 1 Display bl...

Страница 350: ...the internal split resistors When connecting external split resistors this bit must be set to 0 bit 4 BK Display display blanking select bit Selects whether to display or blank LCD When the LCD is blanked BK 1 segment output is nonselective waveform waveforms do not meet display condition bit 3 bit 2 MS1 MS0 Display mode select bits These bits select duty of output waveform from three different du...

Страница 351: ... This bit switches whether P46 SEG20 pin is used as segment output or general purpose port bit 9 SEG1 Segment pin switch bit This bit switches whether P42 SEG16 to P45 SEG19 pins are used as segment output or general purpose port bit 8 SEG0 Segment pin switch bit This bit switches whether P36 SEG12 to P37 SEG13 pins and P40 SEG14 to P41 SEG15 pins are used as segment output or general purpose port...

Страница 352: ... used as normal RAM Tables 14 5 and 14 6 show the relationship between the duty common output and display RAM Figure 14 11 shows the correspondence between display RAM and common segment output pins Address bit 3 bit 2 bit 1 bit 0 SEG00 3960H bit 7 bit 6 bit 5 bit 4 SEG01 bit 11 bit 10 bit 9 bit 8 SEG02 3961H bit 15 bit 14 bit 13 bit 12 SEG03 bit 3 bit 2 bit 1 bit 0 SEG04 3962H bit 7 bit 6 bit 5 b...

Страница 353: ...LCD CONTROLLER DRIVER 14 17 ...

Страница 354: ... to 3967H P42 to P47 P90 P91 00_0011B SEG00 to SEG19 20 pins 3960H to 3969H P46 to P47 P90 P91 00_0111B SEG00 to SEG20 21 pins 3960H to 396AH P47 P90 P91 00_1111B SEG00 to SEG21 22 pins 3960H to 396AH P90 P91 01_1111B SEG00 to SEG22 23 pins 3960H to 396BH P91 11_1111B SEG00 to SEG23 24 pins 3960H to 396BH None Note RAM areas that are not used for LCD display can be used as normal RAM Table 14 6 Re...

Страница 355: ...OM3 pin becomes nonselective output waveform When the LCD display is stopped LCRL MS1 MS0 00B or during reset both common output pins and segment output pins are set to the L level Note When the selected clock for frame cycle generation stops during LCD display the AC generator circuit stops passing the current directly through the liquid crystal element Consequently the LCD display must be stoppe...

Страница 356: ... COM1 pins are used for LCD display when 1 2 duty is used the COM2 and COM3 pins are not used Output waveform on 1 2 bias and 1 2 duty An LCD in which the potential difference between the common output pin and the segment output pin becomes the maximum is set to ON Figure 14 13 shows the output waveform when the display RAM data is shown in Table 14 7 Table 14 7 Example of Display RAM Data Display...

Страница 357: ...ial difference between COM1 and SEGn Potential difference between COM0 and SEGn 1 Potential difference between COM1 and SEGn 1 V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 ON V2 V0 VSS V2 V3 ON V3 ON V2 V0 VSS V2 V3 ON V2 V0 VSS V2 V3 ON V0 to V3 Voltages of V0 to V3 pins 1 cycle 1 frame V3 ON V2 V0 VSS V2 V3 ON V3 ON ...

Страница 358: ...necting and display data 1 2 duty driving type Fig 14 14 Example of LCD Panel Display Data Address 0 to 7 Indicates bits that correspond to display RAM bit 2 bit 3 bit 6 and bit 7 not used Address Example When displaying 5 Display data examples for 0 to 9 LCD Display Display RAM Segment No LCD pannel Address ...

Страница 359: ...3 pin are not used Output waves on 1 3 bias and 1 3 duty An LCD in which the potential difference between the common output pin and the segment output pin becomes the maximum is set to ON Figure 14 15 shows the output waveform when the display RAM data is shown in Table 14 8 Table 14 8 Example of Display RAM Data Display RAM Data Segment COM3 COM2 COM1 COM0 SEGn 1 0 0 SEGn 1 1 0 1 Unused ...

Страница 360: ...tween COM0 and SEGn 1 Potential difference between COM1 and SEGn 1 V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON Potential difference between COM2 and SEGn V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON Potential difference between COM2 and S...

Страница 361: ...3 bit 7 and 2 not used Address Example When displaying 5 Display data examples for 0 to 9 LCD Display Display RAM Segment No LCD panel Address When data starts at bit 4 When data starts at bit 0 When data starts at bit 0 When data starts at bit 4 In the 1 3 duty mode 2 digits are displayed using 3 bytes So data is arranged in two ways starting data at bit 0 of 1st byte and starting data at bit 4 o...

Страница 362: ... for LCD display 1 4 duty Output waveform on 1 3 bias and 1 4 duty An LCD in which the potential difference between the common output pin and the segment output pin becomes the maximum is set to ON Figure 14 17 shows the output waveform when the display RAM data is shown in Table 14 9 Table 14 9 Example of Display RAM Data Display RAM Data Segment COM3 COM2 COM1 COM0 SEGn 0 1 0 0 SEGn 1 0 1 0 1 Un...

Страница 363: ...V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 V2 V1 V0 VSS V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON Potential difference between COM2 and SEGn V3 ON V2 V1 V0 VSS V1 V2 V3 ON V3 ON V2 V1 V0 VSS V1 V2 V3 ON Potential difference between COM2 and SEGn 1 V3 ON V2 V1 V0 VSS V1 V2 V3 ON V0 to V3 Voltages of V0 to V3 pins 1 cycle 1 frame Potential diff...

Страница 364: ...e of LCD panel connecting and display data 1 4 duty driving type Fig 14 18 Example of LCD Panel Display Data Address 0 to 7 Indicates bits that correspond to display RAM Address Example When displaying 5 Display data examples for 0 to 9 LCD Display Display RAM Segment No LCD pannel Address ...

Страница 365: ...LCD CONTROLLER DRIVER 14 29 ...

Страница 366: ...ping Motor Controller 15 3 15 2 Stepping Motor Controller Registers 15 4 15 3 Explanation of Operation of Stepping Motor Controller 15 8 15 4 Precautions at Using Stepping Motor Controller 15 10 15 STEPPING MOTOR CONTROLLER ...

Страница 367: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 15 2 ...

Страница 368: ...e PWM pulse generators and selector logic is designed to control the rotation of the motor A synchronization mechanism assures the synchronous operations of the two PWMs n Block diagram of stepping motor controller Figure 15 1 shows a block diagram of the stepping motor controller Fig 15 1 Block Diagram of Stepping Motor Controller SC PWM1Pn PWM1Mn PWM2Pn PWM2Mn n 0 to 3 CE OE2 OE1 P1 P0 Machine c...

Страница 369: ...3 Address 7 6 5 4 3 2 1 0 3980H 3988H D7 D6 D5 D4 D3 D2 D1 D0 3990H 3998H R W R W R W R W R W R W R W R W X X X X X X X X Address 15 14 13 12 11 10 9 8 3981H 3989H D9 D8 3991H 3999H R W R W X X PWM2 compare register PWC20 PWC21 PWC22 PWC23 Address 7 6 5 4 3 2 1 0 3982H 398AH D7 D6 D5 D4 D3 D2 D1 D0 3992H 399AH R W R W R W R W R W R W R W R W X X X X X X X X Address 15 14 13 12 11 10 9 8 3983H 398B...

Страница 370: ...ut signal for the PWM pulse generators P1 P0 Clock Input 0 0 Machine clock 0 1 1 2 machine clock 1 0 1 4 machine clock 1 1 1 8 machine clock bit 3 CE Count enable bit This bit enables the operation of the PWM pulse generators When it is set to 1 the PWM pulse generators start their operation Note that the PWM2 pulse generator starts the operation one machine clock cycle after the PWM1 pulse genera...

Страница 371: ...e modified values are reflected to the pulse width at the end of the current PWM cycle after the BS bit of the PWM2 select register is set to 1 Always perform word access to this register PWM1 compare register 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W X X X X X X X X 15 14 13 12 11 10 9 8 D9 D8 R W R W X X PWM2 compare register 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ...

Страница 372: ...e at the same time as this automatic reset the BS bit is set to 1 or remains unchanged and the automatic reset is cancelled bits 13 to 11 P2 to P0 Output select bits These bits selects the output signal at PWM2P0 bits 10 to 8 M2 to M0 Output select bits These bits selects the output signal at PWM2M0 bits 5 to 3 P2 to P0 Output select bits These bits selects the output signal at PWM1P0 bits 2 to 0 ...

Страница 373: ...circuit When the counter is started PWCn CE 1 it starts incrementing from 00H on the rising edge of the selected count clock The PWM output waveform is held at H until the counter value matches the value set in the PWM compare register and is held at L until the counter value overflows FFH 00H P0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWCn PWC1n PWC2n PWS1n PWS2n CE TST SC 0 P1 OE1 OE2 Se...

Страница 374: ...next PWM cycle If writing 1 to the BS bit and clearing the BS bit at the beginning of the PWM cycle occur at the same time writing is preferred to clearing and clearing the BS bit will be cancelled Table 15 1 Selection of Motor Drive Signals and Settings of PWM Select Registers 1 and 2 P2 P1 P0 Bit PWM1P Output PWM2P Output M2 M1 and M0 Bit PWM1M Output PWM2M Output 000B L 000B L 001B H 001B H 01X...

Страница 375: ...nd 2 PWS1n and PWS2n can always be accessed When changing the H width of PWM or the PWM output 1 must be written to the BS bit of the PWM select register 2 after or at the same time settings are written to these registers When the BS bit is set to 1 the new setting becomes valid at the end of the current PWM cycle and the BS bit is cleared automatically If writing 1 to the BS bit and resetting the...

Страница 376: ...s of DTP External Interrupt Circuit 16 7 16 4 Registers for DTP External Interrupt Circuit 16 8 16 5 Explanation of DTP External Interrupt Circuit Operation 16 12 16 6 Precautions at Using DTP External Interrupt Circuit 16 16 16 7 Sample Programs for DTP External Interrupt Circuit 16 18 16 DTP EXTERNAL INTERRUPT CIRCUIT ...

Страница 377: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 16 2 ...

Страница 378: ...errupt routine When the EI2 OS is already enabled the DTP function operates automatically transfers the data by EI2 OS and branches to the interrupt processing routine after the specified number of times for data transfer Table 16 1 shows an overview of the DTP external interrupt Table 16 1 Overview of DTP External Interrupt External Interrupt DTP Function Input pins 8 pins P50 INT0 to P53 INT3 P0...

Страница 379: ...pt Number Register Name Address Lower Upper Bank EI2 OS INT0 16 10H ICR02 000B2H FFFFC0H FFFFC1H FFFFC2H INT1 18 12H ICR03 000B3H FFFFB4H FFFFB5H FFFFB6H INT2 20 14H ICR04 000B4H FFFFACH FFFFADH FFFFAEH INT3 22 16H ICR05 000B5H FFFFA4H FFFFA5H FFFFA6H INT4 INT5 24 18H ICR06 000B6H FFFF9CH FFFF9DH FFFF9EH INT6 INT7 26 1AH ICR07 000B7H FFFF94H FFFF95H FFFF96H Can be used when the interrupt request s...

Страница 380: ...of DTP external interrupt circuit Fig 16 1 Block Diagram of DTP External Interrupt Circuit Interrupt request number LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Interrupt request level setting register ELVR Internal data bus Selector Pin P50 INT0 Selector Selector Pin P51 INT1 Selector Pin P52 INT2 Selector Selector Pin P53 INT3 Selector Selector ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 ...

Страница 381: ...pt factor register EIRR IR bit corresponding to the pin is set to 1 Interrupt request level setting register ELVR This register selects the effective level or edge for each pin DTP Interrupt factor register EIRR This register stores the DTP external interrupt factor This register is set to 1 when there is an external interrupt request flag bit corresponding to each pin and there is an effective si...

Страница 382: ... Setting Required to Use Pins P50 INT0 Set to input port DDR5 bit 0 0 P51 INT1 Set to input port DDR5 bit 1 0 P52 INT2 Set to input port DDR5 bit 2 0 P53 INT3 Port 5 I O external interrupt input Set to input port DDR5 bit 3 0 P00 INT4 Set to input port DDR0 bit 0 0 P01 INT5 Set to input port DDR0 bit 1 0 P02 INT6 Set to input port DDR0 bit 2 0 P03 INT7 Port I O external interrupt input CMOS output...

Страница 383: ...e corresponding bit from EN3 to EN0 of the DTP interrupt enable register ENIR are 1 When 0 is written to this bit it is cleared when 1 is written to this bit these bits are not affected Note When output of two or more external interrupt requests is enabled ENIR EN3 to EN0 1 clear only bits for which the interrupt is accepted by the CPU bits from ER7 to ER0 that are set to 1 avoid clearing other bi...

Страница 384: ...pin can be read directly using the port data register irrespective of the state of the external interrupt request enable bit The bits ER3 to ER0 of the DTP interrupt factor register EIRR are set to 1 irrespective of the value of the external interrupt request enable bit when an interrupt factor is detected Table 16 6 Correspondence between DTP Interrupt Control Registers EIRR and ENIR and Each Cha...

Страница 385: ...ese bits select the level or the edge type of the signal that is input to the DTP external interrupt pin and that is a DTP external interrupt factor Each pin is assigned 2 bits Note When the selected detection signal is input to the DTP external interrupt pin 1 is set at the external interrupt request flag bit irrespective of the setting of the DTP interrupt enable register ENIR etc LB7 to LB0 LA7...

Страница 386: ...rol Registers EIRR and ENIR and Each Channel DTP External Interrupt Pin Interrupt Number Bit Number P03 INT7 26 1AH LB7 LA7 P02 INT6 26 1AH LB6 LA6 P01 INT5 24 18H LB5 LA5 P00 INT4 24 18H LB4 LA4 P53 INT3 22 16H LB3 LA3 P52 INT2 20 14H LB2 LA2 P51 INT1 18 12H LB1 LA1 P50 INT0 16 11H LB0 LA0 ...

Страница 387: ...in advance EIRR ER7 to ER0 0 These actions prevent from issuing the interrupt request by mistake when setting the register Switching between external interrupt function and DTP function Switching between the external interrupt function and the DTP function is performed using the ISE bit of the corresponding interrupt control register ICR When the ISE bit is 1 the EI2 OS is enabled making the DTP f...

Страница 388: ...ocessing microprogram is executed When the ISE bit is 1 the EI2 OS processing DTP processing microprogram is executed Figure 16 8 shows the operation of the DTP external interrupt circuit Fig 16 8 Operation of DTP External Interrupt Circuit ELVR 0 DTP External interrupt circuit EIRR ENIR ICR YY Interrupt processing microprogram Interrupt controller Other request CMP IL ILM CMP Interrupt factor ICR...

Страница 389: ...he interrupt request issued from the other resource and the priority of the two or more interrupts generated concurrently etc The CPU determines the interrupt level of the interrupt level mask registers PS ILM2 to ILM0 strength of interrupt level and the interrupt enable bit PS CCR 1 etc When the interrupt request is accepted by the CPU interrupt processing by the internal operation microprogram o...

Страница 390: ...scriptor is performed and the interrupt request flag bit is cleared to prepare for the next request from the pin When the EI2 OS completes transfer of all the data control branches to the interrupt processing routine The external peripheral unit must cancel only the level of the data transfer request signal DTP factor within three machine clocks after the start of the first data transfer Fig 16 9 ...

Страница 391: ...est level setting register ELVR When a level that becomes the interrupt factor is input when the setting is level detection the factor FF in the DTP interrupt factor register EIRR is set to 1 and the factor is held as shown in Figure 16 10 Consequently even when the factor is cancelled the request issued to the interrupt controller remains active if the interrupt request output is already enabled ...

Страница 392: ...ing routine The bit is cleared automatically by the EI2 OS when the DTP function is used Also when the setting is level detection and the level that becomes the interrupt factor remains input the external interrupt request flag bit is reset immediately even when cleared Disable the interrupt request output as needed or cancel the interrupt factor itself CAN WAKEUP function The CAN WAKEUP function ...

Страница 393: ...uest level setting register ER0 EQU EIRR 0 INT0 Interrupt flag bit EN0 EQU ENIR 0 INT0 Interrupt enable bit Main program CODE CSEG START Stack pointer SP etc already initialized MOV I DDR5 00000000B DDR5 set to input AND CCR 0BFH Interrupts disabled MOV I ICR02 00H Interrupt level 0 highest level and EI2OS disabled CLRB EN0 INT0 disabled using ENIR MOV I ELVR 00000010B Rising edge detected for INT...

Страница 394: ...r ISCS EQU 000103H EI2OS status register IOAL EQU 000104H I O address register lower IOAH EQU 000105H I O address register higher DCTL EQU 000106H Data counter lower DCTH EQU 000107H Data counter higher Main program CODE CSEG START Stack pointer SP etc already initialized MOV I DDR0 11111111B DDR0 set to output MOV I DDR5 00000000B DDR5 set to input AND CCR 0BFH Interrupts disabled MOV I ICR02 08H...

Страница 395: ...ed and transfer destination address changed as needed Processing by user Resetting such as ending EI2OS performed Interrupts must be disabled when ending EI2OS RETI Return from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FFC0H Vector set to interrupt 16 10H DSL WARI ORG 0FFDCH Reset vector set DSL START DB 00H Single chip mode set VECT ENDS END START ...

Страница 396: ...17 1 Overview of Delayed Interrupt Generate Module 17 3 17 2 Operation of Delayed Interrupt Generate Module 17 4 17 DELAYED INTERRUPT GENERATE MODULE ...

Страница 397: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 17 2 ...

Страница 398: ...ration of the register for the delayed interrupt generate module delayed interrupt factor generate cancel register DIRR Delayed Interrupt Request Register is shown below bit 15 14 13 12 11 10 9 8 Initial value DIRR address 00009FH R0 0B At a reset the factor cancel state occurs DIRR is a register to control generation cancellation of the delayed interrupt request When 1 is written to the register ...

Страница 399: ...r status PS and when the request level is higher than the ILM bit the CPU starts the hardware interrupt processing microprogram at termination of the instruction being executed As a result the interrupt processing routine for this interrupt is executed When 0 is written to the corresponding bit of DIRR inside the interrupt processing routine the interrupt factor is cleared and the task is switched...

Страница 400: ...18 1 Overview of Timepiece Timer 18 3 18 2 Timepiece Timer Registers 18 4 18 TIMEPIECE TIMER ...

Страница 401: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 18 2 ...

Страница 402: ...perates on the precondition that the MCU oscillation frequency is 4 MHz It operates as a real world timer to provide the real world time information n Block diagram of timepiece timer Figure 18 1 shows the block diagram for the timepiece timer Fig 18 1 Block Diagram of Timepiece Timer 1 2 clock divider 21 bit prescaler CO EN OE WOT OE Sub second register Minute counter CO Second counter CL EN LOAD...

Страница 403: ...LERS HARDWARE MANUAL 18 4 18 2 Timepiece Timer Registers There are five types of registers for the timepiece timer Timepiece timer control register WTCR Sub second data register WTBR Second data register WTSR Minute data register WTMR Hour data register WTHR ...

Страница 404: ...15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R W R W R W R W R W R W R W R W X X X X X X X X WTBR Bit No Sub second data register Address 00395BH Read write Initial value D7 D6 D5 D4 D3 D2 D1 D0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R W R W R W R W R W R W R W R W X X X X X X X X WTBR Bit No Sub second data register Address 00395AH Read write Initial value S5 S4 S3 S2 S1 S0 bit 15 b...

Страница 405: ...nto the counter when the next CO signal is issued from the 21 bit prescaler The UPDT bit is reset by hardware when the value of the counter is rewritten However when setting by software and resetting by hardware occur concurrently the UPDT bit is not reset Writing 0 to the UPDT bit is meaningless When a read modify write instruction is executed for the UPDT bit 0 is read Caution When the UPDT bit ...

Страница 406: ...ub second register is set to 0 the 21 bit prescaler does not operate at all The input clock frequency is designed to be always equal to 4 MHz of the oscillation clock The reload value for the 21 bit prescaler is typically 1E847F in hexadecimal which is equal to 27 56 1 So when two such prescalers are combined clock signals with a cycle of precisely 1 second are issued D20 D19 D18 D17 D16 bit 7 bit...

Страница 407: ...utes 59 seconds or 1 hour 0 minute 0 second or 2 hours 0 minute 0 second Similarly when the MCU operating clock is half the oscillation clock when PLL stopped values read from these registers might be incorrect due to the synchronization of the read and counter operations Consequently when using the second minute hour data register read instructions should be triggered by second interrupts S5 S4 S...

Страница 408: ...D Converter 19 15 19 6 Explanation of 8 10 bit A D Converter Operation 19 16 19 7 Precautions at Using 8 10 bit A D Converter 19 22 19 8 Sample Program 1 for 8 10 bit A D Converter EI2 OS Start in Single shot Mode 19 23 19 9 Sample Program 2 for 8 10 bit A D Converter EI2 OS Start in Continuous Mode 19 25 19 10 Sample Program 3 for 8 10 bit A D Converter EI2 OS Start in Stop Mode 19 27 19 8 10 BIT...

Страница 409: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 19 2 ...

Страница 410: ...rrupt enabled converted data is protected so data is not lost even at continuous conversion Conversion start factor can be selected from software external trigger input falling edge and 16 bit reload timer 1 rising edge and zero detect edge of 16 bit free run timer There are three conversion modes as shown in Table 19 1 Table 19 1 Conversion Modes of 8 10 bit A D Converter Conversion Mode Single C...

Страница 411: ...old circuit D A converter Comparator Controller n Block diagram of 8 10 bit A D converter Fig 19 1 Block Diagram of 8 10 bit A D Converter Input circuit AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 MPX D A converter A D data register Decoder A D control status register 0 higher A D status register 1 lower Prescaler Comparator Sample Hold circuits AVCC AVRH AVSS ADCRH L ADCSH L 16 bit reload timer 1 P50 ADTG φ ...

Страница 412: ...el selector This selector selects the pin to be used from eight analog input pins Sample hold circuit This circuit holds the input voltage selected by the analog channel selector By sample holding the voltage input immediately after A D conversion is started A D conversion is performed without being affected by the fluctuation of the voltage input during A D conversion during voltage comparison D ...

Страница 413: ...O form settings required for using the 8 10 bit A D converter etc Table 19 3 Pins of 8 10 bit A D Converter Function Pin Name Pin Function I O Form Pull up Setting Standby Control Setting I O Port to Use Pins Channel 0 P60 AN0 Channel 1 P61 AN1 Channel 2 P62 AN2 Channel 3 P63 AN3 Channel 4 P64 AN4 Channel 5 P65 AN5 Channel 6 P66 AN6 Channel 7 P67 AN7 Port 6 I O analog input CMOS Output CMOS hyster...

Страница 414: ...ach a pull up resistor to the external pin Also write 0 to the ADER register bit corresponding to the pin When using a pin as an analog input pin write 1 to the ADER register bit corresponding to the pin At this time the value read from the PDR6 register is 0 Internal data bus PDR port data register PDR read PDR write Output latch DDR port direction register Direction latch DDR write DDR read Stan...

Страница 415: ... D Converter The registers for the 8 10 bit A D converter are shown n Registers for 8 10 bit A D converter Figure 19 3 shows the registers for the 8 10 bit A D converter Fig 19 3 Registers for 8 10 bit A D Converter ADCSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 001AH 0021H 0020H 0023H 0022H ADER ADCSL ADCRH ADCRL ...

Страница 416: ...al pin trigger timer or software PAUS Pause Flag Bit This bit is enabled only when EI2 OS is used 0 Indicates A D conversion does not pause 1 Indicates A D conversion pauses INTE Interrupt Request Enable Bit 0 Disables output of interrupt requests 1 Enables output of interrupt requests Interrupt Request Flag Bit INT At Read At Write 0 Indicates A D conversion not ended Clears this bit 1 Indicates ...

Страница 417: ...et to 1 when A D conversion pauses This A D converter has only one A D data register so when reading of the old conversion result by the CPU is not completed when the continuous conversion mode is used the old converted data is lost due to the writing of the new conversion result Therefore when using the continuous conversion mode basically EI 2 OS and automatic transfer of the conversion result t...

Страница 418: ...0 0 0 AN0 pin 0 0 1 AN1 pin 0 1 0 AN2 pin 0 1 1 AN3 pin 1 0 0 AN4 pin 1 0 1 AN5 pin 1 1 0 AN6 pin 1 1 1 AN7 pin Channel number of channel currently being converted Channel number of channel converted just previously MD1 MD0 A D Conversion Mode Select Bits 0 0 Single shot conversion mode 1 conversion can be restarted during operation 0 1 Single shot conversion mode 2 conversion cannot be restarted ...

Страница 419: ...sing the BUSY bit A restart cannot be performed during operation A restart during suspension of the operation is caused by the start factor specified for the STS1 0 bits Note In the one shot conversion continuous conversion and suspend and then convert modes a restart caused by an external software trigger cannot be performed during operation bit 5 bit 4 bit 3 ANS2 ANS1 ANS0 A D conversion start c...

Страница 420: ...s 4 12 µs 16 MHz 1 0 88 machine cycles 5 50 µs 16 MHz 1 1 176 machine cycles 11 0 µs 16 MHz ST1 ST0 Sampling Time Setting Bits 0 0 20 machine cycles 2 5 µs 8 MHz 0 1 32 machine cycles 2 0 µs 16 MHz 1 0 48 machine cycles 3 0 µs 16 MHz 1 1 128 machine cycles 8 0 µs 16 MHz S10 A D Data Bit 0 10 bit resolution mode D9 to D0 1 8 bit resolution mode D7 to D0 S10 ST1 ST0 CT1 CT0 D9 D8 D7 D6 D5 D4 D3 D2 D...

Страница 421: ...The analog input is input sampling time elapses and then after the time set to these bits elapses data of conversion result is determined and stored in bits 9 to 0 of this register Note When 00 for 8 MHz is set when 16 MHz is used the normal analog converted value may not be obtained bit 10 Empty bit bit 9 to bit 0 D9 to D0 The A D conversion result is stored in this register this register is rewr...

Страница 422: ...on result is set to the A D data register ADCR the INT bit of the A D control status register higher ADCSH is set to 1 When the interrupt request is already enabled ADCSH INTE 1 at this point an interrupt request is output to the interrupt controller n 8 10 bit A D converter interrupt and EI 2 OS Table 19 9 8 10 bit A D Converter Interrupt and EI 2 OS Interrupt Control Register Address of Vector T...

Страница 423: ... ending channels are the same ANS ANE conversion is performed for only the channel specified for the ANS bit To perform conversion in the single shot conversion mode the setting shown in Figure 19 7 is needed Fig 19 7 Setting in Single shot Conversion Mode Reference An example of the conversion order in the single shot conversion mode is given below When ANS 000B and ANE 011B AN0 AN1 AN2 AN3 End W...

Страница 424: ... To perform conversion in the continuous conversion mode the setting shown in Figure 19 8 is needed Fig 19 8 Setting in Continuous Conversion Mode Reference An example of the conversion order in the continuous conversion mode is given below When ANS 000B and ANE 011B AN0 AN1 AN2 AN3 AN0 Repeat When ANS 110B and ANE 010B AN6 AN7 AN0 AN1 AN2 AN6 Repeat When ANS 011B and ANE 011B AN3 AN3 Repeat Used ...

Страница 425: ...1 and STS0 bits The setting shown in Figure 19 9 is needed for conversion in the pause conversion mode Fig 19 9 Setting in Pause conversion Mode Reference An example of the conversion order in the pause conversion mode is given below When ANS 000B and ANE 011B AN0 Pause AN1 Pause AN2 Pause AN0 Repeat When ANS 110B and ANE 001B AN6 Pause AN7 Pause AN0 Pause AN1 Pause AN6 Repeat When ANS 011B and AN...

Страница 426: ...ation Flow when Using EI 2 OS When the EI 2 OS is used the function to protect the converted data operates So even during the continuous conversion two or more data items can be transferred reliably to memory without losing any data Start of A D converter Sample Hold Conversion End of conversion Occurrence of interrupt Data transfer Interrupt processing Starting EI2 OS Interrupt clear Specified co...

Страница 427: ...when EI2 OS not used When converted data is stored in the A D data register ADCR the INT bit of the A D control status register higher ADCSH is set to 1 While the INT bit is 1 the A D conversion pauses When the value of the A D data register ADCR is transferred to memory etc using the interrupt routine and then the INT bit is cleared the pause state is canceled Data protection when EI2 OS used Whe...

Страница 428: ...lost when a restart is performed during pause 3 If the A D converter is restarted during pause the queued data is lost EI2 OS set Start of A D continuous conversion Data stored in data register End of first conversion End of second conversion End of third conversion Data stored in data register End of entire conversion EI2 OS completion Start of EI2 OS Pause of A D Start of EI2 OS Start of EI2 OS ...

Страница 429: ... through the gate when the middle level signal is input Precautions at using A D converter via internal timer 16 bit reload timer 1 When starting the A D converter by using the internal timer set using the STS1 and STS0 bits of the A D control status register higher ADCSH At this point set the input value of the internal timer to Inactive L for internal timer When it is set to active operation may...

Страница 430: ...pointer middle order BAPH EQU 000102H Buffer address pointer upper ISCS EQU 000103H EI 2 OS Status register IOAL EQU 000104H I O Address register low order IOAH EQU 000105H I O Address register high order DCTL EQU 000106H Data counter low order DCTH EQU 000107H Data counter high order DDR6 EQU 000016H Port 6 direction register ADER EQU 00001AH Analog input enable register ICR10 EQU 0000BAH A D Con...

Страница 431: ...to P63 set as input pins MOV ADER 00001110B Pins P61 AN1 to P63 AN3 set as analog input pins MOV DCTH 00H MOV ADCSL 0BH Start in single shot mode and convert AN1 to AN3 channels MOV ADCSH 0A2H Software started A D conversion started and interrupts enabled MOV ILM 07H ILM in PS set to level 7 OR CCR 40H Interrupts enabled LOOP MOV A 00H Endless loop MOV A 01H BRA LOOP Interrupt program ED_INT1 MOV ...

Страница 432: ...ter lower BAPM EQU 000101H Buffer address pointer middle BAPH EQU 000102H Buffer address pointer higher ISCS EQU 000103H EI2OS status register IOAL EQU 000104H I O address register lower IOAH EQU 000105H I O address register higher DCTL EQU 000106H Data counter lower DCTH EQU 000107H Data counter higher DDR6 EQU 000016H Port 6 direction register ADER EQU 00001AH Analog input enable register ICR10 ...

Страница 433: ... AN5 set as analog input pins MOV DCTH 00H MOV ADCSL 9DH Start in continuous mode and convert AN3 to AN5 channels MOV ADCSH 0A8H 16 bit reload timer started A D conversion started and interrupts enabled MOVW TMRLR1L 0320H Timer value set to 800 320H 100 µs MOV TMCSR1H 00H Clock source set to 125 ns and external trigger disabled MOV TMCSR1L 12H Timer output disabled interrupts disabled and reload e...

Страница 434: ... 000101H Buffer address pointer middle BAPH EQU 000102H Buffer address pointer higher ISCS EQU 000103H EI 2 OS status register IOAL EQU 000104H I O address register lower IOAH EQU 000105H I O address register higher DCTL EQU 000106H Data counter lower DCTH EQU 000107H Data counter higher DDR6 EQU 000016H Port 6 direction register ADER EQU 00001AH Analog input enable register ICR10 EQU 0000B0H A D ...

Страница 435: ...001000B Pin P63 AN3 set as analog input pins MOV ADCSL 0DBH Start in stop mode and convert AN3 channels MOV ADCSH 0A8H 16 bit reload timer started A D conversion started and interrupts enabled MOVW TMRLR1L 0320H Timer value set to 800 320H 100 µs MOV TMCSR1H 00H Clock source set to 125 ns and external trigger disabled MOV TMCSR1L 12H Timer output disabled interrupts disabled and reload enabled MOV...

Страница 436: ...20 1 Overview of Sound Generator 20 3 20 2 Sound Generator Registers 20 4 20 SOUND GENERATOR ...

Страница 437: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 20 2 ...

Страница 438: ...er decrement counter and tone pulse counter n Block Diagram of Sound Generator Figure 20 1 shows a block diagram of the sound generator Fig 20 1 Block Diagram of Sound Generator Clock input Prescaler S1 S0 8 bit PWM pulse generator CO EN PWM CI CO EN D EN Q Frequency counter Toggle flip flop Amplitude data register DEC Decrement counter CI CO EN Decrement grade register Tone pulse counter CI CO EN...

Страница 439: ...1 INTE INT ST SGCRL Read write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 Amplitude data register 15 14 13 12 11 10 9 8 Bit No Address 00005DH D7 D6 D5 D4 D3 D2 D1 D0 SGAR Read write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 Frequency data register 7 6 5 4 3 2 1 0 Bit No Address 00005CH D7 D6 D5 D4 D3 D2 D1 D0 SGFR Read write R W R W R W R W R W R W R W R W I...

Страница 440: ...cremented by 1 one every time when the decrement counter counts the count of tone pulses from the toggle flip flop specified by the decrement grade register bits 7 to 6 S1 to S0 Operation clock select bits These bits specify the clock input signal for the sound generator S1 S0 Clock Input 0 0 Machine clock 0 1 1 2 Machine clock 1 0 1 4 Machine clock 1 1 1 8 Machine clock bit 5 TONE Tone output bit...

Страница 441: ...NT bit is set to 1 the sound generator signals an interrupt bit 1 INT Interrupt bit This bit is set to 1 when the tone pulse counter counts the count of the tone pulses specified by the tone count register and decrement grade register This bit is reset to 0 by writing 0 Writing 1 has no effect and Read Modify Write instructions always result in reading 1 bit 0 ST Start bit This bit is for starting...

Страница 442: ...d the register value n Frequency Data Register Figure 20 2 shows the relationship between a tone signal and a register value Fig 20 2 Relationship between Tone Signal and Register Value It should be noted that modifications of the register value during operation may alter the duty cycle of 50 depending on the timing of the modification Frequency data register 7 6 5 4 3 2 1 0 Bit No Address 00005CH...

Страница 443: ...And when the register value reaches 00 further decrements are not performed However the sound generator continues its operation until the ST bit is cleared Figure 20 3 shows the relationship between the register value and the PWM pulse Fig 20 3 Relationship between Register Value and PWM Pulse When the register value is set to FF the PWM signal is always 1 Register value 00H 80H FEH FFH One PWM Cy...

Страница 444: ...ores the reload value for the tone pulse counter The tone pulse counter accumulate the count of tone pulses or number of times of decrement operations and when it reaches the reload value it sets the INT bit They are intended to reduce the frequency of interrupts n Tone Count Register The count input of the Tone Pulse counter is connected to the carry out signal from the Decrement counter And when...

Страница 445: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 20 10 ...

Страница 446: ...21 1 Overview of ROM Correction 21 3 21 2 Application Example of ROM Correction 21 6 21 ROM CORRECTION ...

Страница 447: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 21 2 ...

Страница 448: ...nter match and when the compare enable bit is at 1 then the CPU will be forced to execute INT9 instruction n Block diagram of ROM correction Figure 21 1 shows a block diagram of the ROM correction Fig 21 1 Block Diagram of ROM Correction n ROM correction register ROM correction address register Address latch Detection bit Reset Comparitor Set F2 MC 16LX CPU core F2 MC 16LX bus Enable bit Bit No 7 ...

Страница 449: ...he address detect function and indicates its status bits 7 to 4 These are the reserved bits always write 0 bit 3 AD1E Compare Enable 1 This is the PADR1 enable bit When this bit is 1 this module compares the PADR1 register and the address If there is the INT9 instruction is sent to the CPU bit 2 Reserved bit always write 0 bit 1 AD0E Compare Enable 0 This is the PADR0 enable bit When this bit is 1...

Страница 450: ...counter a match and when the compare enable bit is 1 then the CPU will be forced to execute INT9 instruction Note When the address register and the program counter match the internal data bus content will be forced to be 01H so INT9 instruction will be executed Before changing the content of the ad dress register make sure the compare enable bit is 0 If it is changed while the compare enable bit i...

Страница 451: ...rogram by executing the INT9 instruction after address match detection n System structure Fig 21 2 System Structure Example n EEPROM memory map address content 0000H byte count of the patch program No 0 ROM not corrected at 0 0001H bit 7 to bit 0 of program address No 0 0002H bit 15 to bit 8 of program address No 0 0003H bit 24 to bit 16 of program address No 0 0004H byte count of the patch progra...

Страница 452: ...n to the EEPROM n When a program error occurs Figure 21 3 shows an example of ROM correction processing when a program error occurs Fig 21 3 ROM Correction Processing Flow MB90427 Erroneous program Register setting for ROM correction FFFFFFH 000000H RAM ROM 1 2 3 Count of program byte Interrupt generation address Patch program External E2 PROM Data transfer via UART Patch program PC Generation add...

Страница 453: ...program written in the RAM is stored into the RAM defined for each address detect register In this case the INT9 service routine look for this user defined address to jump to the patch program n Reset sequence Fig 21 4 ROM Correction Processing Flow Reset Read the 00H of E2 PROM Read the address 0001H to 0003H E2 PROM MOV PADR0 i MCU j 0000H E2 PROM 0 Read the patch program 0010H to 0090H E2 PROM ...

Страница 454: ... correspoinding program The information stacked during interrupt will be discarded 0000H 000000H Patch program Program address lower 00 Program address middle 00 Program address higher 00 Byte count of patch program 80 Stack area RAM area Patch program RAM register area I O area E2 PROM Erroneous program FFFFH 0090H 0010H 0002H 0003H 0001H 000100H 000400H 000480H 001100H MB90427 FFFFFFH FE0000H FF...

Страница 455: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 21 10 ...

Страница 456: ...22 1 Overview of ROM Mirror Function Select Module 22 3 22 2 ROM Mirror Function Select Register ROMM 22 4 22 ROM MIRROR FUNCTION SELECT MODULE ...

Страница 457: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 22 2 ...

Страница 458: ... in the ROM mirror function select module can be set by the register n ROM mirror function select module n Block diagram of ROM mirror function select module Fig 22 1 Block Diagram of ROM Mirror Function Select Module 15 14 13 12 11 10 9 8 Bit No Address 00006FH MI ROMM Read write W Initial value 1 F2 MC 16LX bus ROM mirror function select register FF bank Address area ROM 00 bank ...

Страница 459: ...nk can also be read in the 00 bank when 1 is set to this bit However this will not be performed when this bit is set to 0 This bit is write only Note Only FF4000 to FFFFFF is mirrorred to 004000 to 00FFFF when ROM mirror function is activated Therefore addresses FFF000 to FF3FFF will not be mirrorred to 00 bank Fig 22 2 Memory Space 15 14 13 12 11 10 9 8 Bit No Address 00006FH MI ROMM Read write W...

Страница 460: ... Classifying CAN Controller Registers 23 11 23 7 Transmission of CAN Controller 23 32 23 8 Reception of CAN Controller 23 34 23 9 Reception Flowchart for CAN Controller 23 36 23 10 How to Use CAN Controller 23 37 23 11 Procedure for Transmission by Message Buffer x 23 38 23 12 Procedure for Reception by Message Buffer x 23 40 23 13 Setting Configuration of Multi level Message Buffer 23 41 23 14 CA...

Страница 461: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 23 2 ...

Страница 462: ...ontroller has the following features Conforms to CAN Specification Version 2 0 Part A and B Supports transmission reception in standard frame and extended frame formats Supports transmission of data frames by receiving remote frames 16 transmission reception message buffers 29 bit ID and 8 byte data Multi level message buffer structure Supports full bit comparison full bit mask and partial bit mas...

Страница 463: ...ransmit receive sequencer Data counter Acceptance filter control BITER STFER CRCER FRMER ACKER TBFX clear TBFX TBFX set clear RBFX set RBFX TBFX set clear RBFX set IDSEL RBFX RBFX TBFX RDLC TDLC IDSEL 0 1 Transmit buffer x decision TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 IDR0 to 15 DLCR0 to 15 DTR0 to 15 RAM LEIR Transmission complete interrupt generation Transmission comple...

Страница 464: ...r RCR R W 00000000 00000000 00004AH 00007AH 00004BH 00007BH Remote request receive register RRTRR R W 00000000 00000000 00004CH 00007CH 00004DH 00007DH Receive overrun register ROVRR R W 00000000 00000000 00004EH 00007EH 00004FH 00007FH Receive interrupt enable register RIER R W 00000000 00000000 003C00H 003D00H 003C01H 003D01H Control status register CSR R W R 00 000 0 0 1 003C02H 003D02H 003C03H...

Страница 465: ...D13H Acceptance mask select register AMSR R W XXXXXXXX XXXXXXXX 003C14H 003D14H 003C15H 003D15H XXXXXXXX XXXXXXXX 003C16H 003D16H 003C17H 003D17H Acceptance mask register 0 AMR0 R W XXXXX XXXXXXXX 003C18H 003D18H 003C19H 003D19H XXXXXXXX XXXXXXXX 003C1AH 003D1AH 003C1BH 003D1BH Acceptance mask register 1 AMR1 R W XXXXX XXXXXXXX n List of CAN WAKE UP control registers Table 23 2 List of CAN WAKE UP...

Страница 466: ...XXXXXX XXXXXXXX 003A26H 003B26H 003A27H 003B27H ID register 1 IDR1 R W XXXXX XXXXXXXX 003A28H 003B28H 003A29H 003B29H XXXXXXXX XXXXXXXX 003A2AH 003B2AH 003A2BH 003B2BH ID register 2 IDR2 R W XXXXX XXXXXXXX 003A2CH 003B2CH 003A2DH 003B2DH XXXXXXXX XXXXXXXX 003A2EH 003B2EH 003A2FH 003B2FH ID register 3 IDR3 R W XXXXX XXXXXXXX 003A30H 003B30H 003A31H 003B31H XXXXXXXX XXXXXXXX 003A32H 003B32H 003A33H ...

Страница 467: ...003B48H 003A49H 003B49H XXXXXXXX XXXXXXXX 003A4AH 003B4AH 003A4BH 003B4BH ID register 10 IDR10 R W XXXXX XXXXXXXX 003A4CH 003B4CH 003A4DH 003B4DH XXXXXXXX XXXXXXXX 003A4EH 003B4EH 003A4FH 003B4FH ID register 11 IDR11 R W XXXXX XXXXXXXX 003A50H 003B50H 003A51H 003B51H XXXXXXXX XXXXXXXX 003A52H 003B52H 003A53H 003B53H ID register 12 IDR12 R W XXXXX XXXXXXXX 003A54H 003B54H 003A55H 003B55H XXXXXXXX X...

Страница 468: ...CR3 R W XXXX 003A68H 003B68H 003A69H 003B69H DLC register 4 DLCR4 R W XXXX 003A6AH 003B6AH 003A6BH 003B6BH DLC register 5 DLCR5 R W XXXX 003A6CH 003B6CH 003A6DH 003B6DH DLC register 6 DLCR6 R W XXXX 003A6EH 003B6EH 003A6FH 003B6FH DLC register 7 DLCR7 R W XXXX 003A70H 003B70H 003A71H 003B71H DLC register 8 DLCR8 R W XXXX 003A72H 003B72H 003A73H 003B73H DLC register 9 DLCR9 R W XXXX 003A74H 003B74H...

Страница 469: ...TR5 R W XXXXXXXX to XXXXXXXX 003AB0H to 003AB7H 003BB0H to 003BB7H Data register 6 8 bytes DTR6 R W XXXXXXXX to XXXXXXXX 003AB8H to 003ABFH 003BB8H to 003BBFH Data register 7 8 bytes DTR7 R W XXXXXXXX to XXXXXXXX 003AC0H to 003AC7H 003BC0H to 003BC7H Data register 8 8 bytes DTR8 R W XXXXXXXX to XXXXXXXX 003AC8H to 003ACFH 003BC8H to 003BCFH Data register 9 8 bytes DTR9 R W XXXXXXXX to XXXXXXXX 003...

Страница 470: ... IDE register IDER Transmit request register TREQR Transmit RTR register TRTRR Remote frame receiving wait register RFWTR Transmission cancel register TCANR Transmission complete register TCR Transmission interrupt enable register TIER Reception complete register RCR Remote request receive register RRTRR Receive overrun register ROVRR Reception interrupt enable register RIER Acceptance mask select...

Страница 471: ...As a result when this bit is 0 it implies that the bus operation is stopped HALT 0 the bus is in the intermission bus idle or a error overload frame is on the bus bit 10 NT Node status transition flag If the node status is changed to increment or from bus off to error active this bit is set to 1 In other words the NT bit is set to 1 if the node status is changed from error active 00 to warning 01 ...

Страница 472: ...it switches from a general purpose port pin to a transmit pin of the CAN controller 0 General purpose port pin 1 Transmit pin of CAN controller bit 2 NIE Node status transition interrupt enable bit This bit enables or disables a node status transition interrupt when NT 1 0 Node status transition interrupt disabled 1 Node status transition interrupt enabled bit 0 HALT Bus operation stop bit This bi...

Страница 473: ...ped HALT 1 after storing the messages To check whether the bus operation has stopped always read the HALT bit n Conditions for canceling bus operation stop HALT 0 By writing 0 to HALT Notes Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALT and continuous 11 bit High levels recessive bits have been input to the ...

Страница 474: ...re used to indicate the message buffer number completing the transmit operation bit 5 RCE Receive completion event bit When this bit is 1 it indicates that receive completion is the last event This bit is set to 1 at the same time as any one of the bits of the receive complete register RCR This bit is also set to 1 irrespective of the settings of the bits of the receive interrupt enable register R...

Страница 475: ...r value In this case Error Passive is indicated for the node status NS1 and NS0 of control status register CSR 11 bits 7 to 0 REC7 to REC0 Receive error counter These are receive error counters REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256 and the subsequent increment is not counted for counter value In this case bus off is indicated for the node status NS1 and NS0 of...

Страница 476: ...ump width set bits 1 and 0 These bits divide the time quanta TQ by RSJ1 to RSJ0 1 for determination of the resynchronous jump width bits 5 to 0 PSC5 to PSC0 Prescaler set bits 5 to 0 These bits divide the input clock by frequency of PSC5 to PSC0 1 for determination of the time quanta of CAN controller The bit time segments defined in the CAN specification and the CAN controller are shown in Figure...

Страница 477: ...gment SYNC_SEG time segment 1 and 2 TSEG1 and TSEG2 and resynchronization jump width RSJ1 and RSJ0 1 frequency division is shown below TQ PSC 1 CLK BT SYNC_SEG TSEG1 TSEG2 1 TS1 1 TS2 1 TQ 3 TS1 TS2 TQ RSJW RSJ 1 TQ For correct operation the following conditions should be met BT 8TQ TSEG2 RSJW 2TQ 1 TSEG1 delay time 2 RSJW 1 2TQ Data processing time 2 Delay time Twice as long as the sum of the bus...

Страница 478: ...he message buffers x during transmission reception n IDE Register IDER 0 The standard frame format ID11 bit is used for the message buffer x 1 The extended frame format ID29 bit is used for the message buffer x Note This register should be set when the message buffer x is invalid BVALx of the message buffer valid register BVALR 0 Setting when the buffer is valid BVALx 1 may cause unnecessary recei...

Страница 479: ...aring is preferred If 1 is written to more than one bit transmission is performed from the lower numbered message buffer x TREQx is 1 while transmission is in the wait state and becomes 0 when transmission is completed or canceled 23 6 9 Transmission RTR Register TRTRR This register stores the RTR Remote Transmission Request bits for the message buffers x n Transmission RTR register TRTRR 0 Data f...

Страница 480: ...mission to the message buffer x At completion of cancellation TREQx of the transmission request register TREQR becomes 0 Writing 0 to TCANx is ignored This is a write only register and its read value is always 0 n Transmission cancel register TCANR Address 003C0DH CAN0 15 14 13 12 11 10 9 8 Bit No Address 003D0DH CAN1 RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8 Read write R W R W R W R W...

Страница 481: ...bles the transmission interrupt by the message buffer x The transmission interrupt is generated at transmission completion when TCx of the transmission complete register TCR is 1 n Transmission interrupt enable register TIER 0 Transmission interrupt disabled 1 Transmission interrupt enabled Address 000047H CAN0 15 14 13 12 11 10 9 8 Bit No Address 000077H CAN1 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8...

Страница 482: ...in message buffer x at same time RCx set to 1 After completion of transmission from message buffer x TCx of transmission complete register TCR 1 Writing 1 to RRTRx is ignored 1 is read when a read modify write instruction is performed Note If setting to 1 and clearing by writing 0 occur at the same time the bit is set to 1 Address 000049H CAN0 15 14 13 12 11 10 9 8 Bit No Address 000079H CAN1 RC15...

Страница 483: ...upt by the message buffer x The reception interrupt is generated at reception completion when RCx of the reception complete register RCR is 1 n Reception interrupt enable register RIER 0 Reception interrupt disabled 1 Reception interrupt enabled Address 00004FH CAN0 15 14 13 12 11 10 9 8 Bit No Address 00007FH CAN1 RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 Read write R W R W R W R W R W R W R ...

Страница 484: ...BYTE0 Address 003C10H CAN0 7 6 5 4 3 2 1 0 Bit No Address 003D10H CAN1 AMS3 1 AMS3 0 AMS2 1 AMS2 0 AMS1 1 AMS1 0 AMS0 1 AMS0 0 Read write R W R W R W R W R W R W R W R W Initial value X X X X X X X X BYTE1 Address 003C11H CAN0 15 14 13 12 11 10 9 8 Bit No Address 003D11H CAN1 AMS7 1 AMS7 0 AMS6 1 AMS6 0 AMS5 1 AMS5 0 AMS4 1 AMS4 0 Read write R W R W R W R W R W R W R W R W Initial value X X X X X ...

Страница 485: ... X X AMR0 BYTE2 Address 003C16H CAN0 7 6 5 4 3 2 1 0 Bit No Address 003D16H CAN1 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 Read write R W R W R W R W R W R W R W R W Initial value X X X X X X X X AMR0 BYTE3 Address 003C17H CAN0 15 14 13 12 11 10 9 8 Bit No Address 003D17H CAN1 AM4 AM3 AM2 AM1 AM0 Read write R W R W R W R W R W Initial value X X X X X AMR1 BYTE0 Address 003C18H CAN0 7 6 5 4 3 2 1 0 Bit No...

Страница 486: ...ge buffer See Section 23 7 At reception when the receive message ID passes through the acceptance filter mechanism for comparing the acceptance masked ID of receive message and message buffer of more than one message buffer the received message is stored in the lowest numbered message buffer See Section 23 8 When the same acceptance filter is set in more than one message buffer the message buffers...

Страница 487: ...d in word unit A write operation in byte unit causes undefined data to be written to the upper byte at writing to the lower byte Writing to the upper byte is ignored This register should be set when the message buffer x is invalid BVALx of the message buffer valid register BVALR is 0 Setting when the buffer is valid BVALx 1 may cause unnecessary receive messages to be stored BYTE0 Address 003A20H ...

Страница 488: ...000 0 to 8 bytes is prohibited Reception Store the data length byte unit of a receive message when a data frame is received RRTRx of the remote frame request receive register RRTRR is 0 Store the data length byte count of a request message when a remote frame is received RRTRx 1 Note A write operation to this register should be performed in word unit A write operation in byte unit causes undefined...

Страница 489: ...Initial value X X X X X X X X BYTE1 Address 003A81H 8x CAN0 15 14 13 12 11 10 9 8 Bit No Address 003B81H 8x CAN1 D7 D6 D5 D4 D3 D2 D1 D0 Read write R W R W R W R W R W R W R W R W Initial value X X X X X X X X BYTE2 Address 003A82H 8x CAN0 7 6 5 4 3 2 1 0 Bit No Address 003B82H 8x CAN1 D7 D6 D5 D4 D3 D2 D1 D0 Read write R W R W R W R W R W R W R W R W Initial value X X X X X X X X BYTE3 Address 00...

Страница 490: ...P control bit This bit controls the internal connection between the RX pin and the INT pin 0 RX pin and INT pin not connected internally The INT pin functions as an ordinary external interrupt pin 1 RX pin and INT pin connected internally The INT pin external interrupt function can no longer be used CWUCR Address 003EH 7 6 5 4 3 2 1 0 Bit No CWU Read write R W R W R W R W R W R W R W R W Initial v...

Страница 491: ...smission request from the CAN controller Canceling by transmission cancel register TCANR A transmission request for message buffer x having not executed transmission during transmission wait state can be canceled by writing 1 to TCANx of the transmission cancel register TCANR At completion of cancellation TREQx becomes 0 Canceling by storing receive message The message buffer x having not executed...

Страница 492: ...quest TREQx 1 Completion of transmission TCx 1 If there are any other message buffers meeting the above conditions select the lowest numbered message buffer Is transmission successful RRTRx 0 TREQx 0 TCx 1 TREQx 0 A transmission complete interrupt occurs A data frame is transmitted A remote frame is transmitted 0 1 YES NO YES NO 0 1 1 0 0 0 1 1 1 0 Is the bus idke RRTRx TRTRx TREQx TI Ex TCANx RFW...

Страница 493: ...a is less than 8 bytes some data is stored in the remaining bytes of the DTRx and its value is undefined When receiving remote frames receive messages are stored only in the IDRx and DLCRx and the DTRx remains unchanged If there is more than one message buffer including Ids that passed through the acceptance filter the message buffer x in which receive messages are to be stored is determined accor...

Страница 494: ... of the transmission request register TREQR becomes 0 immediately before storing the receive message A transmission request for message buffer x having not executed transmission will be canceled Note A request for transmission of either a data frame or remote frame is canceled Processing for reception of remote frame RRTRx becomes 1 If TRTRx of the transmission RTR register TRTRR is 1 TREQx become...

Страница 495: ...art for the CAN Controller Data frame or remote frame starting SOF detected TREQx 1 Completion of reception Determine message buffer x where receive messages to be stored A reception interrupt occurs ROVRx 1 0 1 NO 0 1 Is any message buffer x passing through the acceptance filter found YES YES NO 1 Store the received message in the message buffer x Receive message RRTRx 1 RRTRx 0 TREQx 0 RCx 1 Dat...

Страница 496: ...n acceptance code at reception This setting should be made when the message buffer x is invalid BVALx of the message buffer valid register BVALR is 0 Setting when the buffer is valid BVALx 1 may cause unnecessary receive messages to be stored n Setting acceptance filter The acceptance filter of the message buffer x is set by an acceptance code and acceptance mask setting It should be set when the ...

Страница 497: ...RTRx of the transmission RTR register TRTRR to 0 For remote frame transmission set TRTRx to 1 Setting conditions for starting transmission only for transmission of data frame Set RFWTx of the remote frame receiving wait register RFWTR to 0 to start transmission immediately after a request for data frame transmission is set TREQx of the transmission request register TREQR is 1 and TRTRx of the tran...

Страница 498: ...omplete interrupt In the following cases the transmission request in the wait state is canceled by receiving and storing a message Request for data frame transmission by reception of data frame Request for remote frame transmission by reception of data frame Request for remote frame transmission by reception of remote frame Request for data frame transmission is not canceled by receiving and stori...

Страница 499: ...comes 1 For data frame reception RRTRx of the remote request receive register RRTRR becomes 0 For remote frame reception RRTRx becomes 1 If a reception interrupt is enabled RIEx of the reception interrupt enable register RIER is 1 an interrupt occurs After checking the reception completion RCx 1 process the receive message After completion of processing the receive message check ROVRx of the recep...

Страница 500: ... combined message buffers If the bits of the acceptance mask select register AMSR are set to all bits compare AMSx 1 AMSx 0 0 0 multi level message configuration of message buffers is not allowed This is because all bits compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register RCR so receive messages are always stored in lower number...

Страница 501: ... 0000 000 0 Message receiving 0101 1111 000 0 Message receiving The receive message is stored in message buffer 13 Message receiving The receive message is stored in message buffer 14 Message receiving The receive message is stored in message buffer 15 Message receiving An overrun occurs ROVR13 1 the receive message is stored in message buffer 13 Initialization RCR 1 ROVRR 0 1 0 0 0 Message buffer...

Страница 502: ...rovides the WAKE UP function In this case the INT pin external interrupt function can no longer be used Since the RX1 and INT1 pins share the same pin the WAKE UP function can be used without switching these pins RX Pin Interrupt Function CAN0 RX0 INT0 CAN1 RX1 INT1 n CAN WAKE UP function With the sleep mode set a return can be made from the sleep mode using the CAN receive data Before transition ...

Страница 503: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 23 44 ...

Страница 504: ...ster for Low Voltage and CPU Operation Detection Reset Circuit 24 5 24 4 Operation of Low Voltage and CPU Operation Detection Reset Circuit 24 7 24 5 Cautions when Using Low Voltage and CPU Operation Detection Reset Circuit 24 8 24 6 Sample Program for Low Voltage and CPU Operation Detection Reset Circuit 24 9 24 LOW VOLTAGE AND CPU OPERATION DETECTION RESET CIRCUIT ...

Страница 505: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 24 2 ...

Страница 506: ...ow voltage detection reset circuit continues operating even in the Stop mode so when it detects a low voltage it causes an internal reset and cancels the Stop mode A low voltage reset occurs after writing to the internal RAM The reset output of this circuit is inhibited while an internal reset occurs n CPU Operation detection reset circuit The CPU operation detection reset circuit is a counter tha...

Страница 507: ...a low voltage is detected by comparing the detection voltage value and power supply voltage The voltage comparator operates constantly after power on Detection reset control register for low voltage and CPU operation LVRC The detection reset flag for low voltage and CPU operation is cleared and the CPU operation detection function counter is cleared Reset factor for detection reset circuit for low...

Страница 508: ... read and write Unused X Undefined Initial value RESV0 RESV0 RESV1 RESV1 CL LVRF RESV0 CPUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00111000B Initial value CPU Operation Detection Flag Bit CPUF At Read At Write 0 Indicates no overflow occurs Clears this bit 1 Indicates overflow occurs Does not affect this bit or other bits Low voltage Detection Flag Bit LBRF At Read At Write 0 Indicates no...

Страница 509: ...e CPU operation detection circuit counter is cleared bit 2 LVRF Low voltage detection flag bit When a drop in the power supply voltage is detected this bit is set to 1 At write 0 clears this bit 1 does not affect this bit or other bits An internal reset does not initialize this bit input of an external reset initializes it bit 1 RESV0 Reserved bit Note Always write 0 to this bit bit 0 CPUF CPU Ope...

Страница 510: ...e is executed after the operation stabilization wait time has elapsed and then the program restarts at the address specified for the reset vector n Operation of low voltage detection reset circuit The low voltage detection reset circuit waits for the operation stabilization wait time and then starts low voltage detection Table 24 4 gives the operation stabilization wait time Table 24 4 Operation S...

Страница 511: ...cuit detects a low voltage during the stop mode a reset occurs and the stop mode is cancelled n Cautions when using CPU operation detection reset circuit Circuit operation cannot be stopped using the program The CPU operation detection reset circuit operates continuously after power on Circuit operation cannot be stopped using software Inhibition of reset The CPU operation detection function must ...

Страница 512: ...ion reset circuit is given below n Sample program for low voltage and CPU operation detection reset circuit Processing specifications The CPU operation detection function counter is cleared Sample coding LVRC EQU 000BH Address of detection reset control register for low voltage and CPU operation Main program CSEG CODE SEGMENT MOV LVRC 11110010B CPU operation detection function counter cleared END ...

Страница 513: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 24 10 ...

Страница 514: ...e 25 6 25 4 Flash Memory Control Status Register FMCS 25 8 25 5 Start Automatic Algorithm of Flash Memory 25 10 25 6 Check Execution State of Automatic Algorithm 25 11 25 7 Details of Programming to and Erasing from Flash Memory 25 16 25 8 Cautions when Using Flash Memory 25 22 25 9 Sample Program for 1 Mbit Flash Memory 25 23 25 1 MBIT FLASH MEMORY ...

Страница 515: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 25 2 ...

Страница 516: ...ses automatic program algorithm Embedded Algorithm TM the same manner as MBM29F400TA Erase pause restart function Detects completion of writing erasing using data polling or toggle bit functions Detects completion of writing erasing by CPU interrupts Programming erase count minimum 10 000 times Compatible with JEDEC standard commands Sector erase function any combination of sectors Sector protecti...

Страница 517: ...ircuit and Figure 25 2 gives the flash memory sector configuration n Block diagram for entire flash memory Fig 25 1 Block Diagram for Entire Flash Memory BYTE CE OE WE AQ0 to AQ18 DQ0 to AQ15 INT RY BY BYTE CE OE WE AQ0 to AQ17 AQ 1 DQ0 to DQ15 RY BY RESET F2 MC 16LX bus Write enable interrupt signal issued to CPU RY BY write enable signal Port 0 Port 3 Port 4 COM2 to COM3 SEG0 to SEG11 Flash Memo...

Страница 518: ...sh memory CPU address Writer address FFFFFFH 7FFFFH SA4 16 Kbytes FFC000H 7C000H FFBFFFH 7BFFFH SA3 8 Kbytes FFA000H 7A000H FF9FFFH 79FFFH SA2 8 Kbytes FF8000H 78000H FF7FFFH 77FFFH SA1 32 Kbytes FF0000H 70000H FEFFFFH 6FFFFH SA0 64 Kbytes FE0000H 60000H Writer address The writer address is equivalent to the CPU address where data is programmed to flash memory by a parallel writer This address is ...

Страница 519: ...placed in the FE to FF banks of the CPU memory space and like the normal mask ROM can be read accessed or program accessed from the CPU via the flash memory interface circuit Programming to erasing from of the flash memory is performed by an instruction issued from the CPU via the flash memory interface circuit Consequently in this mode re programming can be performed even when the MCU is soldered...

Страница 520: ... to A6 9 SEG6 AQ16 A15 10 SEG7 CE CE 12 SEG8 OE OE 13 SEG9 WE WE 14 to 15 SEG10 to SEG11 AQ17 to AQ18 A16 to A17 16 P36 BYTE BYTE 17 P37 RY BY RY BY 18 to 22 P40 to P44 AQ8 to AQ12 A7 to A11 24 to 26 P45 to P47 AQ13 to AQ15 A12 to A14 49 MD0 MD0 A9 VID 50 MD1 MD1 RESET VID 51 MD2 MD2 OE VID 85 to 92 P00 to P07 DQ0 to DQ7 DQ0 to DQ7 77 RST RESET RESET Not supported DQ8 to DQ15 ...

Страница 521: ...Automatic Algorithm 1 is always read when the read modify write RMW instruction is used 0 Programming and erasing 1 Programming and erasing terminated interrupt request issued bit 5 WE Write Enable This bit enables writing to the flash memory area When this bit is 1 data is programmed to a flash memory area after issuing a command sequence see the Flash Memory Automatic Algorithm to the FE to FF b...

Страница 522: ...nsumption mode operation at internal operating frequency of 4 MHz or less 10 Low power consumption mode operation at internal operating frequency of 8 MHz or less 11 Low power consumption mode operation at internal operating frequency of 10 MHz or less 00 Normal power consumption mode operation at internal operating frequency of 16 MHz or less Note Both the RDYINT and RDY bits never change at the ...

Страница 523: ...dress Data Address Data Address Data Read Reset 1 FxXXXX XXF0 Read Reset 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA even PD word Chip erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 Sector erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA even XX30 Sector Erase suspend Input of address Fxxx...

Страница 524: ...equence flag DQ7 DQ6 DQ5 DQ3 Whether programming and chip sector erasing are being executed can be checked using any of the hardware sequence flags or the RDY bit of the flash memory control register FMCS After the completion of programming and erasing the flash memory returns to the read reset state At actual program creation whether or not programming and erasing have been completed should be ch...

Страница 525: ... the end of the auto programming algorithm causes flash memory to output the value of bit 7 at the address specified by the address signal At chip sector erasing During executing chip and sector erasing algorithms read access is made at the current sector during sector erasing and irrespective of the specified address during chip erasing Flash memory then outputs 0 Similarly when read access is at...

Страница 526: ...ithm or the chip sector erase algorithm the flash memory outputs 1 and 0 alternately each time a read is performed toggle state irrespective of the address indicated by the address signal When read access is performed continuously at completion of the automatic programming algorithm or the chip sector erasing algorithm the flash memory stops the bit 6 toggle operation and outputs bit 6 DATA 6 of t...

Страница 527: ...g the automatic programming algorithm or the automatic chip sector erasing algorithm 0 is output when the time required for programming erasing is within the specified time 1 is output when the time required for programming erasing exceeds the specified time Since this is irrelevant to whether the automatic algorithm is currently being executed or is complete this can be used to determine whether ...

Страница 528: ...ng irrespective of the address indicated by the address signal of the sector to which the command is issued it outputs 1 when the wait period for sector erasing is exceeded When the erasing algorithm is currently being executed by the data polling function or toggle bit function with this flag 1 it indicates that an internally controlled erasing has already started The next sector erase code write...

Страница 529: ...p erase Any data erasing Sector erase Sector erasing suspention Sector erasing resumption 25 7 1 Read reset State in Flash Memory This section explains the procedure for issuing the read reset command to place flash memory in the read reset state n Read reset state in flash memory Flash memory can be placed in the read reset state by sending the read reset command in the command sequence table see...

Страница 530: ...polling algorithm DQ7 or toggling DQ6 is not terminated and the flash memory is considered faulty the timing limit exceeding flag DQ6 is considered as being in error or data 1 is assumed to have been written When data is read in the read reset state the data remains 0 Only erasing enables data 0 to be set to data 1 All commands are ignored during writing If a hardware reset occurs during writing d...

Страница 531: ...abled Program command sequence 1 FxAAAA XXAA 2 Fx5554 XX55 3 FxAAAA XXA0 Program address Program data Data polling DQ7 Internal address read Internal address read Timing limit DQ5 FMCS WE bit 5 Programming disabled Data polling DQ7 Last address Next address Start Programming completed Programming error Data Data Data 0 1 Check by hardware sequence flag Data ...

Страница 532: ...to any one of the accessible even addresses in the sixth cycle a 50 µs sector erasing wait is started When erasing more than one sector the sector erase code 30H is written to the sector address following the above sequence Precautions at specifying multiple sectors Sector erasing is started after a 50 µs period waiting for sector erasing is completed after the last sector erase code has been writ...

Страница 533: ...X55 Internal address read 1 Internal address read1 Timing limit DQ5 FMCS WE bit 5 Erasing disabled Last sector Next address Start Erasing completed Erasing error N Y Y 0 1 N Internal address read 2 Toggle bit DQ6 Data 1 DQ6 Data 2 DQ6 Internal address read2 Toggle bit DQ6 Data 1 DQ6 Data 2 DQ6 Code input to sector to be erased 30H Is any sector to be erased Sector erase timer DQ3 Y N Y N 0 1 Inter...

Страница 534: ...address can be an any address in the flash memory At suspending the erase a second erasing suspend command is ignored When the sector erasing suspend command is input during the sector erasing wait period the sector erase wait state ends immediately the erase is interrupted and the erase stop state occurs When the erase suspend command is input during the sector erase after the sector erase wait p...

Страница 535: ...CPU may occur because the flash memory unit is not initialized and the automatic algorithm continues being executed As a result the flash memory unit may be prevented from entering the read state when the CPU starts executing the sequence after the reset is made inactive The reset conditions must be inhibited during programming erasing of the flash memory Programming access to flash memory Read ac...

Страница 536: ...ss FE0000H sector SA0 and output to PDR2 5 Erase programmed sector SA0 6 Output verification that data is erased Conditions Count of bytes transferred to RAM 100H 256B Completion of programming and erasing checked by Timing limit exceeding flag DQ5 Toggle bit flag DQ6 RDY FMCS Action taken at error Output High level to P00 to P07 Issue reset command RESOUS IOSEG ABS 00 Definition of RESOUS I O seg...

Страница 537: ...00H Data input port MOV DDR1 00H MOV PDR2 00H Data output port MOV DDR2 0FFH Transfer flash programming erasing program FFBC00H to RAM address 700H MOVW A 0700H Transfer destination RAM area MOVW A 0BC00H Transfer destination source address location where program stored MOVW RW0 100H Count of bytes to be transferred MOVS ADB PCB Transfer 100V from FFBC00H to 000700H CALLP 000700H Jump to address w...

Страница 538: ... command 1 MOVW ADB COMADR2 0055H Program command 2 MOVW ADB COMADR1 00A0H Program command 3 MOVW A RW0 00 Program input data RW0 to flash memory RW2 MOVW RW2 00 A WRITE Waiting time check ERROR occurs when the time limit exceeding check flag is set and toggling MOVW A RW2 00 AND A 20H DQ5 time limit check BZ NTOW Time limit over MOVW A RW2 00 AH MOVW A RW2 00 AL XORW A XOR of AH and AL 1 if value...

Страница 539: ... toggling is underway MOVW A RW2 00 AND A 20H DQ5 time limit check BZ NTOE Time limit over MOVW A RW2 00 AH During programming from DQ6 are alternately MOVW A RW2 00 AL output High and Low level every reading XORW A XOR of AH and AL 1 if DQ6 value invalid indicating programming underway AND A 40H Is DQ6 toggle bit High BNZ ERROR If yes go to ERROR Erasing end check FMCS RDY NTOE MOVW A FMCS AND A ...

Страница 540: ...6 3 Example of Serial Write Connection Power Supplied from the Writer 26 7 26 4 Example of Minimum Connection to the Flash Microcontroller Programmer User Power Supply Used 26 9 26 5 Example of Minimum Connection to the Flash Microcontroller Programmer Power Supplied from the Writer 26 11 26 EXAMPLES OF MB90F428 A SERIAL WRITE CONNECTION ...

Страница 541: ...MB90420 5 A SERIES F2 MC 16LX FAMILY 16 BIT MICROCONTROLLERS HARDWARE MANUAL 26 2 ...

Страница 542: ...ite mode the CPU internal operation clock signal is one multiple of the PLL clock signal frequency Therefore because the oscillation clock frequency becomes the internal operation clock signal the oscillator used for serial rewriting is 1 MHz to 16 MHz P00 P01 Write program activation pins RSTX Reset pin SIN1 Serial data input pin SOT1 Serial data output pin SCK1 Serial clock input pin UART1 is us...

Страница 543: ...lash microcontroller programmer power supplied from the writer Table 26 2 Flash Microcontroller Programmer System Configuration Manufactured by Yokogawa Digital Computer Ltd Model Function AF220 AC4P Model with internal Ethernet interface 100 V to 220 V power adapter AF210 AC4P Standard model 100 V to 220 V power adapter Unit AF110 AC4P Single key model 100 V to 220 V power adapter AZ221 PC AT RS2...

Страница 544: ...pply used Fig 26 1 Example of Serial Write Connection for MB90F428 A User Power Supply Used 10 kΩ 10kΩ P00 MD0 MD1 TMODE TAUX3 TICS MD2 AF220 AF210 AF110 flash microcontroller programmer MB90F428 A TAUX User 10 KΩ 19 12 23 10 User system X0 X1 1 MHz to 16 MHz 10 kΩ VSS VCC GND SCK1 SOT1 SIN1 TRXD TTXD TCK 13 27 6 Pins 3 4 9 11 16 17 18 20 24 25 and 26 are open DX10 28S Right angle type Connector H...

Страница 545: ... the control circuit shown in the figure below is required in the same as P00 The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing Connect the AF200 while the user power is off User 10 KΩ MB90F428 A Write control pin AF220 AF210 AF110 write control pin AF220 AF210 AF110 TICS pin ...

Страница 546: ...om the writer Fig 26 2 Example of Serial Write Connection for MB90F428 A Power Supplied from the Writer 10 kΩ 10kΩ P00 MD0 MD1 TMODE TAUX3 TICS MD2 AF220 AF210 AF110 flash microcontroller programmer MB90F428 A TAUX User 10 KΩ 19 12 23 10 User system X0 X1 1 MHz to 16 MHz 10 kΩ VSS VCC GND SCK1 SOT1 SIN1 TRXD TTXD TCK 13 27 6 Pins 4 9 11 17 18 20 24 25 and 26 are open DX10 28S Right angle type Conn...

Страница 547: ...equired in the same as P00 The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing Connect the AF200 while the user power is off When supplying programming power from AF200 do not short circuit the programming power and user power User 10 KΩ MB90F428 A Write control pin AF220 AF210 AF110 write control pin AF220 AF210 AF110 TICS pin ...

Страница 548: ...lash microcontroller programmer Fig 26 3 Example of Minimum Connection to the Flash Microcontroller Programmer User Power Supply Used 10 kΩ MD1 MD2 AF220 AF210 AF110 flash microcontroller programmer MB90F428 A User system MD0 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 for serial rewrite 0 for serial rewrite 1 for serial rewrite User circuit P00 10 kΩ P01 User circuit 0 for serial rewrite 1 for serial rewrite...

Страница 549: ...ser system the control circuit shown in the figure below is required The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing Connect the AF200 while the user power is off User 10 KΩ MB90F428 A Write control pin AF220 AF210 AF110 write control pin AF220 AF210 AF110 TICS pin ...

Страница 550: ...re set as described below Fig 26 4 Example of Minimum Connection to the Flash Microcomputer Programmer Power Supplied from the Writer 10 kΩ MD1 MD2 AF220 AF210 AF110 flash microcontroller programmer MB90F428 A User system MD0 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 for serial rewrite 0 for serial rewrite 1 for serial rewrite User circuit P00 10 kΩ P01 User circuit 0 for serial rewrite 1 for serial rewrite...

Страница 551: ...below is required The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial writing Connect the AF200 while the user power is off When supplying programming power from AF200 do not short circuit the programming power and user power User 10 KΩ MB90F428 A Write control pin AF220 AF210 AF110 write control pin AF220 AF210 AF110 TICS pin ...

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