Freescale Semiconductor MCF54455, Справочное руководство

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UART Modules
32-17 Freescale Semiconductor
32.4.1.1 Programmable Divider
As Figure 32-17 shows, the UART n transmitter and receiver can use the following clock sources:
• An external clock signal on the DT n IN pin.
When not divided,
DT n IN
provides a synchronous
clock; when divided by 16, it is asynchronous.
• The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by
the 16-bit value programmed in UBG1
n and UBG2 n . See Section 32.3.11, “UART Baud Rate
Generator Registers (UBG1n/UBG2n) .”
The choice of DTIN or internal bus clock is programmed in the UCSR.
Figure 32-17. Clocking Source Diagram
NOTE
If DT n IN is a clocking source for the timer or UART, that timer module
cannot use DT n IN for timer input capture.
32.4.1.2 Calculating Baud Rates
The following sections describe how to calculate baud rates.
32.4.1.2.1 Internal Bus Clock Baud Rates
When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and
then passes through the 16-bit divider of the concatenated UBG1
n and UBG2 n registers. The baud-rate
calculation is:
Using a 133-MHz internal bus clock and letting baud rate equal 9600, then
Eqn. 32-1
UART
On-Chip
TIN

1

16
16-bit
Divider

32
TIN
Clocking sources programmed in UCSR
Timer Module
Internal
Tx
Rx
Rx Buffer
Tx Buffer
f
sys/2
Bus Clock
U n RXD
U n TXD
DT n IN
DT n OUT
Divider
133 MHz
32 x 9600
 
------------------------------- 433 decimal
 
0x 01 B0 hexadecimal
 
= = =