Freescale Semiconductor MCF54455, Справочное руководство

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Universal Serial Bus Interface – On-The-Go Module
Freescale Semiconductor 10-5
• Doze — The processor stops the system clocks to the USB OTG module, but the 60 MHz
transceiver clock remains active. In doze mode, detection of resume signaling initiates a restart of
the module clocks.
10.2 External Signal Description
Table 10-2 describes the external signal functionality of the USB OTG module.
NOTE
The ULPI signals are multiplexed with the FEC module. This section
describes the signal functions when in ULPI mode; refer to
Chapter 16, “Pin
Multiplexing and Control,” for more details.
Table 10-2. USB OTG Signal Descriptions
Signal I/O Description
On-chip FS/LS transceiver
USB_CLKIN I Optional 60 MHz clock source. This signal is also used for the input clock from a ULPI PHY.
USB_DM I/O Data minus. Output of dual-speed transceiver for the USB OTG module.
State
Meaning
Asserted—Data 1
Negated—Data 0
Timing Asynchronous
USB_DP I/O Data plus. Output of dual-speed transceiver for the USB OTG module.
State
Meaning
Asserted—Data 1
Negated—Data 0
Timing Asynchronous
USB_PULLUP O Enables an external pull-up on the USB_DP line. This signal is controlled by the
UOCSR[BVLD] bit.
State
Meaning
Asserted—Pull-up enabled. UOCSR[BVLD] set.
Negated—Pull-up disabled. UOCSR[BVLD] cleared.
Timing Asynchronous
ULPI Interface
ULPI_DIR I Direction. ULPI_DIR controls data bus direction. When PHY has data to transfer to USB port,
it drives ULPI_DIR high to take ownership of the bus. When the PHY has no data to transfer,
it drives ULPI_DIR low and monitors the bus for link activity. The PHY pulls ULPI_DIR high
when the interface cannot accept data from the link. For example, when PHY’s PLL is not
stable.
State
Meaning
Asserted—PHY has data to transfer to the link.
Negated—PHY has no data to transfer.
Timing Synchronous to USB_CLKIN or ULPI_CLK.