Z8OQT
4.
Check for
operation of
the interval timer and timing circuits by
observing pin
18
of
U20
(m)
for
a low-going
output
each time a write
operation
is
executed.
If the
m
signal
is
present, check
for
a SYNC
signal
at
pin
10
of
the shielded cable
connector,
and for a UUT ON signal
at pin
19
of the
PCB-to-PCB connector.
The absence of these signals
allows the pod
to
communicate with the mainframe,
but
prevents the
latches
from detecting addresses, data,
and control signals sent to the
UUT (or self test socket).
Failure
of these signals may also prevent write
data
from reaching the UUT.
5-11.
SELF TEST CODE
2
If
a self test produces a failure code
of
2,
failure of one or more of the
control
lines
is
indicated.
To
check each
of
the
control
lines, use the mainframe
to
perform
a BUS TEST. Refer
to
the heading Bit Assignment ~Control Lines,
located in Section
3,
for
interpretation
of the mainframe message.
5—12.
SELF TEST CODE
3
(APPLIES TO
9000
SERIES
ONLY)
If
a self test produces a failure code of
3,
failure of one or more status line buffers
is
indicated.
Each
of
the
status
(forcing) lines, which have the ability to
interrupt
or otherwise interfere with
microprocessoroperation,
are selectively buffered
from
the microprocessor.
Buffering of
the
RESET,
NMI,
BUSRQ, and WAIT lines
is
accomplished by
means of gates which are enabled or inhibited by
port
B
outputs of
the
RAM-I/
0-Interval Timer.
5-13. Troubleshooting an Inoperative Pod
NOTE
The
followingparagraphs
reference three distinct areas
of
the
pod
identified
as the
Processor
Section, the UU
Tlnterface
Section,
and
the Timing Circuits. Components
that
make up these sections are
identified in the Theory
of
Operation,
presented
in
Section
4.
A
pod
is
considered inoperative when the performance of self test, or any other
mainframeoperation, produces
a
pod timeout
message. Such a message results
from
a lack
of
response by the
pod to mainframe
commands. Since it
is
the
function
of the
Processor
Section to
respond to
mainframe commands, lack of
response indicates failure of the
Processor
Section.
Prepare
to
troubleshoot
the inoperative pod
as
follows:
I.
Disassemble the pod. Refer to Disassembly.
5-14
Содержание 9000A-Z80QT
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Страница 18: ...ZBOQT Figure 2 3 Connection 0 Interface Pod to UUT...
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Страница 76: ...Z8OQT MP10 H 2 9000A Z8OQT 5071 Figure 6 1 9000A 2800T Intertace Pod Final Assembly...
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Страница 85: ...ZBOQT QLVLSNXVI 9 Figure 7 1 A11 Processor PCB Assembly...
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Страница 89: ...ZBOQT DEVICE 6ND PINS 14 Figure 7 1 A11 Processor PCB Assembly cont 7 7...
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