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ZBOQT

Table

3-1.

280 Signals (cont)

SIGNAL NAME

DESCRIPTION

MREQ Line

W—Fl

Line

RFSH Line

HALT Line

AIT Line

and

Lines

The

MREQ

output

identifies a memory

access

operation

progress. The 280 places

MREQ

logic

low

during any memory

access

operation.

addition,

MREQ is

placed

a high impedance state

during

DMA

operations. See

BUSRQ.

The

IOFlQ

output identifies any l/O operation

progress. When

lORQ is low,

address

lines A0

A15

contain a

valid

l/O

port

address. The

IORQ line is

also

used

conjunction

with

the

line

as an interrupt

acknowledge. When the 280 acknowledges an

inter-

rupt, both lines

are

driven low.

low.

The

725

output

pulled

low

indicatethat

the 280

ready to read

data

via

the data lines from either

memory or an l/O device, as identified

the

MREQ

IORQ line.

addition,

Fl_D

placed

a high

impedance state during

DMA'

operations. See

BUSRQ.

The

output

pulled

low

to indicate that the 280

ready to write data

via

the data lines to either

memory or an l/O device,

asﬂantified

the

MREQ

IORQ line. ln

addition,

WR is

placed

high

impedance state during

DMA

operations. See

BUSRQ.

The

RFSH

output

a control signal which may be

used

conjunction with the

MREQ line

to refresh

dynamic memories. When

RFSH is

pulled

low

the

MREQ

signal and address lines

may

be used

refresh dynamic memories.

The

HALT

output

pulled

low

following the

execution

a halt instruction. During the halt state,

the 280 continuously executes a

NOP

instruction

order to maintain memory refresh

activity.

The

WAlT line is

an input which, when placed at a

logic

low level,

causes the

Z80

to enter a wait state.

During the wait state,

the

280 inserts clock pulses to

extend

the

cycle time as required

the external

logic selecting the wait state.

The

line

is an

input which permits external

interrupt of

the

280 as long as interrupts are not

disabled and the

BUSRQ line is

not at a logic

low.

The

line

a non-maskable interrupt input

which cannot be disabled.

Содержание 9000A-Z80QT

Страница 2: ...d and bill you for reasonable repair cost SERVICE If a failure occurs send the product postage prepaid to the closest Service Center with a description of the difficulty Repairs will be made or the pr...

Страница 3: ...ASSIGNMENT 3 4 3 4 Introduction 3 4 3 5 Bit Assignment Status Lines 3 4 3 6 User Writable Control Lines 3 4 3 7 Bit Assignment A Control Lines 3 5 3 8 Address Space Assignment 3 5 3 9 FORCINGAND INTER...

Страница 4: ...DETECTIONLIMITS 3 20 THEORY OF OPERATION 4 1 4 INTRODUCTION 4 1 4 2 GENERALPOD OPERATION 4 1 4 3 Processor Section 4 1 4 3 Processor Section 4 1 4 4 UUT Interface Section 4 4 4 5 Timing Section 4 4 4...

Страница 5: ...E OF CONTENTS continued SECTION TITLE PAGE 6 LIST OF REPLACEABLE PARTS 6 1 6 1 INTRODUCTION 6 1 6 2 HOW TO OBTAIN PARTS 6 1 7 SCHEMATIC DIAGRAMS 7 1 APPENDIX A USING THE Z8OQT POD FROM TL l PROGRAMS A...

Страница 6: ......

Страница 7: ...rite Test Addresses 3 8 3 4 Quick RAM Test Addresses and Status Codes 3 12 3 5 Quick ROM Test Addresses and Status Codes 3 14 3 6 Quick Fill and Verify Addresses and Status Code 3 18 5 l Self Test Fai...

Страница 8: ...to 9000 Series 2 3 Connection of Interface Pod to 9100 Series 2 3 Connection of Interface Pod to UUT 2 4 280 Pin Assignments 3 3 General Block Diagram 4 2 Detailed Block Diagram 4 6 HandshakingSignal...

Страница 9: ...ons interrupt handling timing size of memory space and size of I 0 space AppendixA contains informationaboutusing this pod with 9100 Series Digital Test Systems in TL l programs 1 2 DESCRIPTION OF INT...

Страница 10: ...uld result from O Incorrectly inserting the ribbon cable plug in the UUT microprocessor socket O UUT faults that place potentially damaging voltages on the UUT microprocessorsocket The over voltage pr...

Страница 11: ...ZBOQT m0 umwkz_ O m0 mmm _ 2_ O _ 2 m 5 0m mmOmn Fwy 00m mOmmwOOmaOm QE w mu2_ _2 memw 005 m0 Doom mXDJE Flgure 1 1 Relationship of Interface Pod 1 3...

Страница 12: ...nput High Voltage 2 0V min 5 0V max Output Low Voltage 0 4V max with lol 1 8 mA Output High Voltage 2 4V min with Ioh 250 pA Trlstate Output Leakage Current 20 uA High Level Input Current 20 uA typ wi...

Страница 13: ...2 cm Widex18 550m Deep 1 3 in High x 4 0 in Wide x 7 4 in Deep Weight 0 68 kg 1 5 lbs Environmenl STORAGE 40 to 70 C RH 95 OPERATlNG 0 to 25 C RH 95 25 to 40 C RH 75 40 to 50 C RH 45 Protecllon Class...

Страница 14: ......

Страница 15: ...ction Remove the original from the floppy drive and insert the copy into the system USERDISK Each time the mainframe is reset the database is read from the oppy disk Place the original floppy disk in...

Страница 16: ...rame 4 Performa self testofthe pod as described in Section 5 ofthis manual 5 With UUT power off unplug the microprocessor from the UUT 6 On the pod turn the self test socket thumbwheel to release the...

Страница 17: ...Z8OQT Figure 2 1 Conneclion oi Interface Pod to 9000 Series POD CONNECTS HERE Figure 2 2 Connection oi lnterlace Pod to 9100 Series...

Страница 18: ...ZBOQT Figure 2 3 Connection 0 Interface Pod to UUT...

Страница 19: ...DESCRIPTION Address Lines A0 A15 Data lines DO D7 The 16 address linesare designated A0 throughA15 The address lines are tri state outputs and may be logic high logic low or floated by the Z80 to a hi...

Страница 20: ...pulled low to indicate that the 280 is ready to write data via the data lines to either memory or an l O device as antified by theMREQ or IORQ line ln addition WR is placed in a high impedance state d...

Страница 21: ...d floats all tri state bus signals to the high impedance state The BUSRQ line is an input which when placed at a logic low level causes the 280 to relinquish control of the system bus by floating the...

Страница 22: ...tatus line and a 0 indicates a logic low status line To determine which characters of the display correspond to specific status lines refer to Table 3 2 This table shows that each line is assigned a b...

Страница 23: ...peration the HALT line can be driven but the BUSAK line cannot the 9000 Series mainframe displays the message CTRLERR 00000001 LOOP The BUSAK line is represented by bit number 0 A 9100series mainframe...

Страница 24: ...cing lines and interrupts Forcing lines are those lines which when made active force the microprocessorinto some specific action Forcing lines for the 280 are BUSRQ WAIT and RESET Pulling BUSRQ or WAI...

Страница 25: ...cularly useful for enhanced viewing of signal traces on an oscilloscope synchronized to the TRIGGER OUTPUT pulse available on the rear panel of the mainframe Unlike ordinary mainframe looping function...

Страница 26: ...e NOTE Special addresses mentionedin the followingparagraphs are also validfor 9100 Series mainframes However they are not necessary because the 9100 Series provides softkeys to directly access these...

Страница 27: ...nd 9100 Series mainframes are presented separately after a description of the tests 3 16 Quick RAM Test Description The Quick RAM Test allows the operator to test RAM address blocks more quickly than...

Страница 28: ...ry ROM test nor is error reporting in the Quick ROM test as extensive However the Quick ROM test can detect inactive data bits and the checksum can be used to detect a faulty ROM device with a high de...

Страница 29: ...st results The status codes and their meanings are shown in Table 3 4 Read onlyspecial addresses in the F0 20XX range contain additionalinforma tion about the Quick RAM test including errors and recor...

Страница 30: ...Busy addressdecoding check B2 Busy pattern verify check CO Complete no errors F0 Failed read write error F1 Failed address decoding error F2 Failed pattern verity error READ ONLY ADDRESS FUNCTION F0...

Страница 31: ...be greater than the starting address For example to specify a Quick ROM test over ROM addresses 0000 through 0FFF do the following two operations WH TE 30 0000 0 WRITE 30 0FFF 1 The Quick ROM test be...

Страница 32: ...0D 300E 3010 3014 30F0 Start address LSB Start address 2nd byte Start address MSB End address LSB End address 2nd byte End address MSB Checksum LSB Checksum MSB Hex mask inactivebits Most recent code...

Страница 33: ...f the default of test press the right arrow key then select 2 7 Press ENTER to start the test 8 When the BUSY indicator goes off and no error messages are returned the UUT has passed 3 21 Using the 91...

Страница 34: ...special addresses described below for 9000 Series or to the display 9100 Series 0 Quick Fill and Verify specified by 3 combines Quick Fill and Quick Verify into one step 3 23 Using the 9000 Series fo...

Страница 35: ...f the addresses used errors and other information The special addresses for Quick Fill and Verify are described in Table 3 6 To determine if Quick Fill or Verifyis still in progress or what the test r...

Страница 36: ...illegal data in command A2 Aborted illegal address in command BO Busy filling B1 Busy verifying CO Complete no errors F0 Failed verify READ ONLY ADDRESS FUNCTION F0 4000 F0 4001 F0 4002 F0 4004 F0 40...

Страница 37: ...n The pod differences tend to make marginal UUT problems more obvious and easier to troubleshoot Different UUT and pod operating conditionsthat may reveal marginal problems are described in the paragr...

Страница 38: ...UUT bus the pod provides equal to or better than normal 280 current drive capability All pod inputs and outputs except the clock are TTL compatible 3 32 POWER FAILURE DETECTION LIMITS A power sensing...

Страница 39: ...ce to the mainframe These elements comprise a small computer system which receives mainframe commands and directs all pod operationsduring execution All reset non maskable interrupts and other disrupt...

Страница 40: ...ANDSH IKE 0 A LINES _ I I I MICRO PROCESSOR I RAM I I L ___________ I r_ __________ I TIMING I I SECTION I I INTERVAL I I TIMER I I I I I I I I TIMING DISABLERAM mm m I I CIRCUITS ENABLE BUFFERS I I I...

Страница 41: ...S BUFFERS AND I LOGIC LEVEL SENSING I STATUS SIGNALS A STATUS I CONTROL SIGNALS _ CONTROLA I ENABLE I BUFFERS UUT INTERFACE 1 SECTION J UUT MICRO PROCESSOR SOCKET UUT CLOCK 6 POWER UUT SENSING V CIRCU...

Страница 42: ...primary function of the timing section is to cause the microprocessor to work with either the Processor Section or the UUT Interface Section at a time pre determined by the microprocessoritself Causin...

Страница 43: ...o change from controlling the Processor Section to controlling the UUT Interface Section but does not return control back to the Processor Section In addition the RESET NMI WAIT and BUSRQ inputsare en...

Страница 44: ...v a 0 v E TIMER cl g EMULATOR D 3 u U16 U29 z I 2 4 ROM MICRO O PROCESSOR a U2 DISABLE u U5 o I gs Ar STATUS DRIVE SIGNALS LINES CONTROL BUFFERS I O J PORT B STATUS ENABLE __ RUN UUT IRQ TIMER OUT UU...

Страница 45: ...IRCCVJIT I NW N 20535 5 UUT 2 _ 1 ADDRESS U3 U5 BAO BA15 v92 _ v A SYNC j g 0 7v_ E D AT AWI LE 4 LAO LA7 LATCHES A2 A3 5 ADDRESS A DDHIEN U4 U6 2 ADDLOEN DECODER OE O BLATCHEN E U7 __ CONTEN E 4 3v S...

Страница 46: ...formthe steps necessary to assemble the UUT address ready the data to be written and perform housekeeping operations associated with the command In addition the routinedirects the actualwrite and read...

Страница 47: ...torin series with the line and a pairof clipping diodes The diodes clip the data line at zero and 5 volts The data lines are also equipped with logic leveldetection circuits one circuit per line The d...

Страница 48: ...m 0mm m NEMI F FWZ_ _ q 828 55 55 mo o mm mthOImmamDOmh 0 DO Eomn h o _ _ _ wDOn Q mm Dm _m_0m_m _ Q DZ _ _OO F sz_ _ _ QmOij OZ O P O 0232200 _ a m0m_m m_ wmmI 00m 0 MESH 225 20 h o mo man 252 200 Fl...

Страница 49: ...UT ON DO D7 UUT ILVRITE I 2 O LATCH UUT ON 5 MAINFRAM E SYNC OUT r E 1 _ 0 4w TalTl T2 F MEM READ WRITE rIt M1 T3 T1 7LT REFRESH x pc ADDRESSX ADDRESS x MEMORY AC DRESS PC AD F_ l _ L DATA OUT LA1 77...

Страница 50: ...tems equipment As described for the data lines the address lines are equipped with logic level detectioncircuits one circuit per line The detection circuits consist of a series of latches coupled to t...

Страница 51: ...UT The ProcessorSection is disabled at this point by the address decoder U7 and U31 which receives the UUT ON signal generated by the timing circuits With the address decoder disabled the ROM and RAM...

Страница 52: ...croprocessor in place of the microprocessor removed to facilitate pod connection The RUN UUT mode continues until a RESET signal is received from the mainframe The RESET signal from the mainframecause...

Страница 53: ...derfor the pod to accept and execute self test commands issuediby the mainframe NOTE Self test does not examine the podfor all conceivable faults and may indicate an okay pod when not completely opera...

Страница 54: ...et by operating the adjacent thumbwheel Insert the ribbon cable plug into the socket and close the socket using the thumbwheel 3 Turn the mainframeon and press BUS TEST to initiate self test 4 If the...

Страница 55: ...007 Unexpected response when disabling enableable lines 2 Open the pins of the self test socket by operating the adjacent thumbwheel Insert the ribbon cable plug into the socket and close the socket u...

Страница 56: ...epair should have a rating of 25 watts or less to prevent overheating the PCB assembly 5 4 TROUBLESHOOTING 5 5 introduction Pod failure is usually identifiable from the mainframe display Two types of...

Страница 57: ...to the mainframe Service Manual for a list of Fluke Service Centers 5 6 Pod Detective or Inoperative Before attempting to repair a faulty pod the level of failure should be determined A faulty pod can...

Страница 58: ...ZBOQT _ u w L g 51 g i w a gggi i a w aagaww imw am n g my 3 _ mag 3 W w awmmawa kgg owo Flgure 5 1 lntertace PCB Non Component Side...

Страница 59: ...clock signal to drive the pod 0 5V dc UUT power to check the UUT power sensing circuit Instead of connection to a known good UUT the ribboncable connector may be connected to the selftest socket on t...

Страница 60: ...e fact that a self test can be performed indicates operation of the Processor Section since operationofthe Processor Section is necessary for mainframe pod communication With the Processor Section pro...

Страница 61: ...nsparent to the user 9100 SERIESPOD SELF TEST FAILURE OPERATOR ACTIONS TO CODE POD OPERATION RECREATE TEST 0 Reset Pod Cycle Power Read special address READ SPECIAL ADDR OOFFO OFFOOFFO If a powerfail...

Страница 62: ...F TO SPECIAL ADDR 00080 address00000080 38 Enable first enableable SETUP POD ENABLE BUSRQ ON line verify pod timeout occurs Disablefirst enableable SETUP POD ENABLE BUSRQ OFF line again 39 Enable seco...

Страница 63: ...al is pulled low at test socket the self test socket by UUT cable pin 29 GND 2002 VCC pin on self test None check VCC line through the UUT is high no power fail cable and the POWERFAIL signal 2006 Pod...

Страница 64: ...test socket sends the upper address byte to the data lines During self test read operations at OFFO and FOOF take place Use any address containingknowndata if using some other UUT 3 a If the mainframe...

Страница 65: ...roceed as follows 1 Check the operation of the UUT power sensing circuit by verifying the 5V UUT supply at the ribboncable connector and 0V on the Power Fail line Check the Power Fail line ofthe PCB t...

Страница 66: ...roduces a failure code of 3 failure of one or more status line buffers is indicated Each ofthe status forcing lines which have the ability to interrupt or otherwise interfere with microprocessoroperat...

Страница 67: ...re in hexadecimal notation Refer to the Theory of Operation in Section 4 and the schematic diagram in Section 7 to troubleshoot an inoperative pod using the following steps as a guide 1 Reset the pod...

Страница 68: ...ZSOQT 5 VOLT 5 VOLT SUPPLY SUPPLY INOPERATIVE POD TROUBLESHOOTER SECOND POD PROBE Figure 5 3 Troubleshooting an lnoperatlve Pod 5 16...

Страница 69: ...rol line latch 5000 UUT Address line latch low byte 6000 UUT Status line latch 7000 Table 5 5 ZBOQT lntertace Pod Quick ROM Checksum ROM ADDRESS RANGE CHECKSUM SOFTWARE VERSION 0000 to 1FFF 1 0 _ b Pe...

Страница 70: ...0 to address 2094 to reset the timer then writing OF to address 209C Verify that the m output at U20 pin 18 goes low in response to the second write operation 10 Check for the occurrence of the UUT ON...

Страница 71: ...te the two PCB assemblies except to replace components Figure 5 1 shows the location ofeach component on the lower PCB assembly relative to the accessible non component side of the board 4 Ifit is not...

Страница 72: ......

Страница 73: ...rt Number 6 Total Quantity of Components Per Assembly 7 Recommended quantity This entry indicates the recommended number of spare parts necessary to support one to five instruments for a period of 2 y...

Страница 74: ...5 Printed Circuit Board Part Number and Revision Letter 6 Instrument Model and Serial Number A Recommended Spare Parts Kit foryourbasic instrument is available from the factory This kit contains those...

Страница 75: ...quo oH mmHo m 9 mmvmmm nm o HUmemmmm muHoo aoomN N 29 vammw H pzmz acomsnmooom H 2H meHmm moamHmmm z com mHmcu H m HNHmmm MmHn omzidmuomm NH m2 pommqw uHmmm szov st Hmommmuo HH m mh wmm m HHz sz onHm...

Страница 76: ...Z8OQT MP10 H 2 9000A Z8OQT 5071 Figure 6 1 9000A 2800T Intertace Pod Final Assembly...

Страница 77: ...m m a Hmso qaamH oH oHomHQNmmmmmmzp mmamm zH xm mozu 0H uHom ma u oz z aoNzH N o so aaam uH UHOm mam o po HHEmH uH 0Hom ma u ozd HnmzH N o 20 HaamH oH QHOm ma u mo aamzH N o po HaHmH uH NmzmHDNS BHm...

Страница 78: ...wmmmm mmNHo ImQOUI Mukm mmhz omomm s m uom wm ol N zm q amwmu H w HN m sz om uH ammuom pm ax m m sz ov uH ammuom m ax Famwvw sz mm uH amxu0m N ox mumo h uHom mAm zm 3 moon mqu w m qaamg uH am a mmmovn...

Страница 79: ...rm 3330 E hum dam Z O H F D G 0 9000A 2800T 1601 O O 3 a an on a E Hun ago 2 mu I mg I I m n gun a H Hmam m 33 45 I mg 3 ml 2 a II II I I E wig 1 5H II IImII ENE a BB I O I I mFmE EE O Figure 6 2 A11...

Страница 80: ...hov mnmczm 3 moon mzHH m n HaamH uH h o wmmmm H m m a vwmmmm uma wnm mamemnm z m m a Hauo mozo uH w v m a HHNpqw madam M s m ux mam Haaoo HHHmH uH m m H a mmHmm sm o wm Hm o mo mum m m bNmNHV 3m o ama...

Страница 81: ...H HmcmmloHumum m mmumo c s oo m H thFO womam Nwmmo Imoool xqmm mum a mu mh m a eznoz mosmHmzmmB mmu mm H m x wmmmav sz mH oH ameOm 0H ax Hmvvmw m ax Hmvvmv sz ou vH amxoom w m 1H ox uozus 1 uu u onamH...

Страница 82: ...ZBOQT N 1 r3 1 m 5 2 2 In 0 1 B J a U to Us a U l N o 9 3 1 _ 5 1 5 4 O N 3 O E 1 e r0 3 2 9000A 280 1672 Figure 6 3 A12 Interface PCB Assembly...

Страница 83: ...FIGURE 7 1 7 2 ZBOQT Section 7 Schematic Diagrams TABLE OF CONTENTS TITLE PAGE All Processor PCB Assembly 7 2 A12 Interface PCB Assembly 7 8 7 1...

Страница 84: ...Z8OQT E 3 mwmdwwwwmi o a u n v u 2 as MLVLSI IQ 23333329...

Страница 85: ...ZBOQT QLVLSNXVI 9 Figure 7 1 A11 Processor PCB Assembly...

Страница 86: ...ZBOQT H H u Chum 55 ixu m3m V V v 0 A0 m v mmmcaa 5 5 taxman th XEH 35me 9 02 hww m4mm Nu W tho mu m uw m 7 4...

Страница 87: ...ZBOQT W manna I l ml Uu mzornu l u mm m m J_ L zwzbu 22b thhKme lzmur x IkJ I xx m n taxmamm ahmmwzm iku xn lag xzw h n Flgure 7 1 A11 Processor PCB Assembly cont 7 5...

Страница 88: ...2800T 7 6 m V L LOl D INPUTS PAL U27 LOGIC Flgure 1 1 A11 Processor PCB Assembly cont OUTPUTS 15...

Страница 89: ...ZBOQT DEVICE 6ND PINS 14 Figure 7 1 A11 Processor PCB Assembly cont 7 7...

Страница 90: ...Z8OQT LA SELF HOLD LO BUSAK 7 8 C 2 5 5v 22A if 22L l clz Em 0531 00 463 EEF tzaF L _____________ _J...

Страница 91: ...N OHMS l 1w 5CL ALL CAPACITORS ARE w MICROFARADS A E J UDQ UDI UDZ UDa U04 UDS UDE UD I UAqs UA I UAZ UAS UA4 UAS Mb UAY UAB UA9 UAIO UAII Ume UNI UNA UA 5 50 bN wu1 MM 9 CIGIOOO9F ALEZQ J 9000A Z80 1...

Страница 92: ......

Страница 93: ...D SOFTWARE VERSION NUMBER To determinethe Pod software version you performa read at a special address Fromthe front panel press the READkey the SPECIALsoftkey and the right arrow key Then enter addres...

Страница 94: ...ven though BUSRQ and WAIT are Pod specific enable is not so these use the built in syntax podsetup enable BUSRQ off podsetup enable WAIT off l These examples are all 2800 Pod specific podsetup I_REG S...

Страница 95: ..._ A it 45 nS A tcal _ 7 a DATA LATCHED HERE SPECIFIEDEDGE Figure A 1 9000A 2800T Pod Address Sync Timing Once the reference edge is found an offset is applied to that edge to determine where in time t...

Страница 96: ..._FILLTL 1 program is that the TL 1 program only allows the Quick Fill and Verifytest to be executed in the mainframe s current address space Arguments ADDR This is the starting address of the Quick Fi...

Страница 97: ...fault is included for consistency with the way 9000 series testers handle the Quick FILL program and should never be seen in normal operation reason Illegal function type The value of the FUNCTION ar...

Страница 98: ...Quick RAM test see Section 3 14 The major difference between the test that Section 3 14 describes and the test that is implemented by the QWK RAM TL l program is that the TL l program only allows the...

Страница 99: ...tion reason Illegal function type The value of the FUNCTION argument does not conform to the restrictions detailed above reason Illegal space The current address space is not legal for this test reaso...

Страница 100: ...ADDR argument does notconform to the specification detailed above reason Illegal space The current address space is not legal for this test reason Space not found The addressspace that the mainframe i...

Страница 101: ...ies testers handle the Quick ROM program and should never be seen in normal operation reason Illegal data The value of the DATA argument does not conform to the restrictions detailed above reason Ille...

Страница 102: ...be inactive Returns A checksum of the area of memory that was tested This checksum is unrelated to the signature that is generated by the regular ROM test QWK_WR This programmay be used to put the po...

Страница 103: ...ionsthat can result from Z80QT pod operation Handlers for most faultconditions are based on one ofthe mask types listed underthe heading Bit Definitions of Fault Masks further on in this Appendix 0 Fa...

Страница 104: ...ped signals Mapped signals have a 1 value to indicate an active faulty or otherwise signi cant condition A value of 0 represents the absence of a significant condition for that signal Table A 3 Addres...

Страница 105: ...Bit Signal Pin No 0 D0 14 1 D1 15 2 D2 12 3 D3 8 4 D4 7 5 DS 9 6 D6 10 7 D7 13 8 unused 63 Table A 5 Control Signal Mapping to Fault Masks Control signal fault mask format 000000000000000000000000000...

Страница 106: ...lmLh bODNA O Bit 63 Pod Signal VVAFT BUSRQ NBA INT RESET unused unused PWRFNL unused Status signal fault mask lormat 000000O0000000000000000000O00000000000OOOOOOOXXXXXXXXXXXXXXXX Bit 7 Bit 0 Status s...

Страница 107: ...fault on All I fault pod_addr_tied mask 0000G0000060000000000000000000060006 00060B0 000 000010006000 000 l Raise built in data drivability fault on D7 I fault pod_data_tied mask 00 000006000000000GG...

Страница 108: ......

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