11 PROGRaMMaBle TiMeR
S1C63003/004/008/016 TeChniCal Manual
Seiko epson Corporation
11-5
(Rev. 1.1)
In the event counter mode, the clock is supplied to Timer 0/Timer 2 from outside the IC, therefore, the settings of the
count clock frequency select register PTPS0[3:0]/PTPS2[3:0] becomes invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the pulse polarity
select register PLPUL_A/PLPUL_B. When "0" is written to the PLPUL_A/PLPUL_B register, the falling edge is
selected, and when "1" is written, the rising edge is selected. The count down timing is shown in Figure 11.4.1.
EVIN_A/EVIN_B input
Count data
n
n-1 n-2
n-3
n-4 n-5 n-6
PLPUL_A/PLPUL_B
EVCNT_A/EVCNT_B
0
1
1
PTRUN0/PTRUN1
4.1 Timing chart in event counter mode
Figure 11.
The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on the external
clock (EVIN_A/EVIN_B). This function is selected by writing "1" to the timer function select register FCSEL_A/
FCSEL_B.
When the noise rejector is enabled, an input pulse width for both low and high levels must be 0.98 msec
*
or more to
count reliably. The noise rejector allows the counter to input the clock at the second falling edge of the internal 2,048
Hz
*
signal after changing the input level of the EVIN_A/EVIN_B input terminal. Consequently, the pulse width of
noise that can reliably be rejected is 0.48 msec
*
or less. (
*
: when f
OSC1
= 32.768 kHz)
Figure 11.4.2 shows the count down timing with noise rejector.
Counter
input clock
*
2
Count data
n
n-1
n-2
n-3
EVIN_A/EVIN_B input
2,048 Hz
*
1
*
1
When f
OSC1
= 32.768 kHz
*
2
When PLPUL_A/PLPUL_B register is set to "0"
4.2 Count down timing with noise rejector
Figure 11.
The operation of the event counter mode is the same as the normal timer except it uses the EVIN_A/EVIN_B input
as the count clock. Refer to "11.3 Basic Counter Operation" for basic operation and control.
PWM mode (Timers 0–3)
11.5
[S1C63004/008/016]
Each timer of the S1C63004/008/016 can generate a PWM waveform. When using this function, write "1" to the
PTSELx register to set the timer to PWM mode.
The compare data register CDx[7:0] is provided for each timer to control the PWM waveform. In PWM mode, the
timer compares data between the down counter and the compare data register and outputs the compare match signal if
their contents are matched. At the same time a compare match interrupt occurs. Furthermore, the timer output signal
rises with the underflow signal and falls with the compare match signal. As shown in Figure 11.5.1, the cycle and duty
ratio of the output signal can be controlled using the reload data register and the compare data register, respectively, to
generate a PWM signal. Note, however, the following condition must be met: RLD (reload data) > CD (compare data)
and CD
≠
0. If RLD
≤
CD, the output signal is fixed at "1" after the first underflow occurs and does not fall to "0."
The generated PWM signal can be output from the TOUT_A (P11) or TOUT_B (P23) terminal (see Section 11.8).
