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aPPenDiX C POWeR SaVinG
aP-C-2
Seiko epson Corporation
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
This section describes clock systems that can be controlled via software and power-saving control details. For more
information on control registers and control methods, refer to the respective peripheral circuit sections.
System SleeP (all clocks stopped)
• Execute the SLP instruction (CPU)
Execute the SLP instruction when the entire system can be stopped. The CPU enters SLEEP mode and the
OSC1 and OSC3 oscillation circuits stop. This also stops all peripheral circuits using clocks. Starting up the
CPU from SLEEP mode is therefore limited to startup using a port (described later).
System clock
• Clock source selection (oscillation circuit)
Select between OSC3 and OSC1 for the system clock source. Reduce current consumption by selecting the
OSC1 clock when low-speed processing is possible.
Control register: CLKCHG
Default setting: CLKCHG = "0" (operated with the OSC1 clock)
• OSC3 oscillator circuit stop (oscillation circuit)
Operate the oscillation circuit comprising the system clock source. Where possible, stop the other oscillation
circuit. You can reduce current consumption by using OSC1 as the system clock and stopping the OSC3 oscil-
lation circuit.
Control register: OSCC
Default setting: OSCC = "0" (OSC3 oscillation off)
CPu clock
• Execute the HALT instruction (CPU)
Execute the HALT instruction when program execution by the CPU is not required—for example, when only
the display is required or for interrupt standby. The CPU enters HALT mode and suspends operations, but the
peripheral circuits maintain the status in place at the time of the HALT instruction, enabling use of peripheral
circuits for timers and interrupts. You can reduce power consumption even further by suspending unnecessary
oscillation circuit and peripheral circuits before executing the HALT instruction. The CPU is started from
HALT mode by an interrupt from a port or the peripheral circuit operating in HALT mode.
Peripheral circuit clocks
• Stop clock supply to the peripheral circuits (clock manager)
The S1C63003/004/008/016 incorporates a clock manager to control the clock supply to the peripheral circuits.
Stop the clock supply to the unused peripheral circuits to reduce current consumption.
The table below lists the peripheral circuits of which the operating clock can be stopped.
1.1 Peripheral circuits with clock control
Table C.
Peripheral circuit/function
Stop control
Frequency selection Clock control register
FOUT output
Possible
Possible
FOUT[3:0]
Key input interrupt noise rejector (P00 to P03)
Possible
Possible
NRSP0[1:0]
Key input interrupt noise rejector (P10 to P13)
*
3
Possible
Possible
NRSP1[1:0]
LCD system voltage regulator (booster clock)
Possible
–
VCCKS[1:0]
Serial interface
*
3
Possible
Possible
SIFCKS[2:0]
R/F converter
Possible
Possible
RFCKS[2:0]
Programmable timer 0
Possible
Possible
PTPS0[3:0]
Programmable timer 1
*
3
Possible
Possible
PTPS1[3:0]
Programmable timer 2
*
3
Possible
Possible
PTPS2[3:0]
Programmable timer 3
*
1
Possible
Possible
PTPS3[3:0]
Clock timer
Possible
–
RTCKE
Stopwatch timer
Possible
–
SWCKE
Sound generator
Possible
–
SGCKE
Integer multiplier
*
2
Possible
–
MDCKE
*
1 S1C63016 only
*
2 S1C63008/016 only
*
3 S1C63004/008/016 only
• Use low-speed clocks (clock manager)
Reduce current consumption by setting the clock for the peripheral circuit that supports clock frequency selec-
tion as low as possible.