Epson S1C63003, Техническое руководство

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6 inTeRRuPT COnTROlleR
S1C63003/004/008/016 TeChniCal Manual
Seiko epson Corporation
6-5
(Rev. 1.1)
CALR INTRFC ;call Interrupt RFC
RETI
INT_DUMMY:
RETI
;******************************************************************************
;** Interrupt RFC **
;******************************************************************************
.org 0x800
INTRFC:
LDB %yl,P5CTL0@l
LDB %xl,ITC_RFC1@l
LD [%y],[%x] ;Port Output
RET
i/O Memory of interrupt Controller 6.5
Table 6.5.1 shows the I/O addresses and the control bits for controlling interrupts.
5.1 Control bits of interrupt controller Table 6.
Address Register name R/W Default Setting/data Function
FFE1H D3 0 (
*
3) R – (
*
2) – Unused
D2
eiRFe
R/W 0 1 Enable 0 Mask Interrupt mask register (RFC error)
D1 eiRFR R/W 0 1 Enable 0 Mask Interrupt mask register (RFC REF completion)
D0
eiRFS
R/W 0 1 Enable 0 Mask Interrupt mask register (RFC SEN completion)
FFE2H D3 0 (
*
3) R – (
*
2) – Unused
D2 0 (
*
3) R – (
*
2) – Unused
D1 eiPT0 R/W 0 1 Enable 0 Mask Interrupt mask register (PT0 underflow)
D0
eiCTC0 ( *
6) R/W 0 1 Enable 0 Mask Interrupt mask register (PT0 compare match)
FFE3H
(
*
6)
D3 0 (
*
3) R – (
*
2) – Unused
D2 0 (
*
3) R – (
*
2) – Unused
D1 eiPT1 R/W 0 1 Enable 0 Mask Interrupt mask register (PT1 underflow)
D0
eiCTC1
R/W 0 1 Enable 0 Mask Interrupt mask register (PT1 compare match)
FFE4H
(
*
6)
D3 0 (
*
3) R – (
*
2) – Unused
D2 0 (
*
3) R – (
*
2) – Unused
D1 eiPT2 R/W 0 1 Enable 0 Mask Interrupt mask register (PT2 underflow)
D0
eiCTC2
R/W 0 1 Enable 0 Mask Interrupt mask register (PT2 compare match)
FFE5H
(
*
4)
D3 0 (
*
3) R – (
*
2) – Unused
D2 0 (
*
3) R – (
*
2) – Unused
D1 eiPT3 R/W 0 1 Enable 0 Mask Interrupt mask register (PT3 underflow)
D0
eiCTC3
R/W 0 1 Enable 0 Mask Interrupt mask register (PT3 compare match)
FFEAH
(
*
6)
D3 0 (
*
3) R – (
*
2) – Unused
D2 0 ( * 3) R – ( * 2) – Unused
D1 0 (
*
3) R – (
*
2) – Unused
D0 eiSiF R/W 0 1 Enable 0 Mask Interrupt mask register (Serial I/F)
FFEBH D3 eiK03 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY03<P03>)
D2 eiK02 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY02<P02>)
D1 eiK01 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY01<P01>)
D0 eiK00 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY00<P00>)
FFECH
( * 6)
D3 eiK13 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY13<P13>)
D2 eiK12 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY12<P12>)
D1 eiK11 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY11<P11>)
D0 eiK10 R/W 0 1 Enable 0 Mask Interrupt mask register (KEY10<P10>)
FFEDH D3 eiRun (
*
6) R/W 0 1 Enable 0 Mask Interrupt mask register (SW direct RUN)
D2 eilaP ( * 6) R/W 0 1 Enable 0 Mask Interrupt mask register (SW direct LAP)
D1 eiSW1 R/W 0 1 Enable 0 Mask Interrupt mask register (Stopwatch 1 Hz)
D0 eiSW10 R/W 0 1 Enable 0 Mask Interrupt mask register (Stopwatch 10 Hz)
FFEEH D3 eiT3 (
*
6) R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 16 Hz)
D2 eiT2 R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 32 Hz)
D1 eiT1 (
*
6) R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 64 Hz)
D0 eiT0 ( * 6) R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 128 Hz)
FFEFH D3 eiT7 R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 1 Hz)
D2 eiT6 R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 2 Hz)
D1 eiT5 (
*
6) R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 4 Hz)
D0 eiT4 R/W 0 1 Enable 0 Mask Interrupt mask register (Clock timer 8 Hz)