SoM-A5D36 User Manual
Revision 1.30 © 2015
- 10 -
2.4.4
Ethernet
The SoM-A5D36 provides a Micrel KSZ9031 10/100/1000 Ethernet PHY IC on board. Carrier designers need
only run these lines through the appropriate magnetics layer to have a functional Ethernet connection.
Remember the RX and TX lines are differential pairs and need to be routed as such.
The LED/configuration pin
s’ state at reset determines the PHY address. These pins are pulled to set the
PHY address to 0x01 by default. The address can be changed by pulling these lines to a different value on
a custom carrier board. This can be especially useful if an additional PHY is added to a custom carrier by
accessing the RMII pins described below.
Table 5: Ethernet
SODIMM
Pin#
SoM
Pin Name
KSZ9031
Pin Name
Description
12
GIG D-
TXRXD_N
GIG Ethernet D- pin
14
GIG D+
TXRXD_P
GIG Ethernet D+ pin
13
GIG C-
TXRXC_N
GIG Ethernet C- pin
15
GIG C+
TXRXC_P
GIG Ethernet C+ pin
16
Ethernet_Rx-/GIG B-
TXRXB_N
Low differential Ethernet receive
line
18
Ethe/GIG B+
TXRXB_P
High differential Ethernet receive
line
17
Ethernet_Tx-/GIG A-
TXRXA_N
Low differential Ethernet transmit
line
19
Ethe/GIG A+
TXRXA_P
High differential Ethernet transmit
line
38
LED_LINK/CFG_2
LED2/PHY_AD1
Ethernet Link LED/Configuration
pin
39
LED_ACT/CFG_3
LED1/PHY_AD0
Ethernet Activity LED/Configuration
pin
Table 6: RMII Ethernet Interface
SODIMM
Pin#
SoM
Pin Name
Processor
Pin Name
Description
99
COMA_DTR
ETX0
RMII Transmit Data 0
100
COMA_DSR
ETX1
RMII Transmit Data 1
101
COMA_RI
ERX0
RMII Receive Data 0
104
COMB_CTS
ERX1
RMII Receive Data 1
105
COMB_RTS
ETXEN
RMII Transmit Control
37
Card_Detect
ECRSDV
RMII Receive Control
116
GPIO2
ERXER
RMII Receive Error
117
GPIO3
EREFCK
RMII Reference Clock
118
GPIO4
EMDC
RMII Management Data Clock
119
GPIO5
EMDIO
RMII Management Data IO
