Elnec DATAMAN-40PRO, Руководство пользователя

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PG4UW
Device / Test
This command executes a test with device selected from list of supported devices (e.g. static
RAM) on programmers, which support this test.
Device / IC test
This command activates a test section for ICs separated by type to any libraries (on
distribution CD). First select an appropriate library, wished device and then a mode for test
vectors run (LOOP, SINGLE STEP). Control sequence and test results are displayed to LOG
WINDOW. In case of need is possible to define the test vectors directly by user. Detailed
description syntax and methods of creation testing vectors is described in example_e.lib file,
which is in programs installation folder.
Note.
Testing of IC is done using test vectors at some (pretty low) speed. The tests by test vectors
can not detect all defects of the chip. Other words, if IC test report "FAIL", then device is
defective. But if is "PASS" reported, it mean the chip passed our tests, but still might not pass
the tests, that check other - mainly dynamic - parameters of the tested IC.
Because the rising/falling edges of programmers are tuned for programming of chips, it may
happen the test of some chips fails, although the chips aren't defective (counters for
example).
Device / JAM/VME/...Player
Jam STAPL was created by Altera® engineers and is supported by a consortium of
programmable logic device (PLD) manufacturers, programming equipment makers, and test
equipment manufacturers.
The Jam™ Standard Test and Programming Language (STAPL), JEDEC standard JESD-71,
is a standard file format for ISP (In-System Programming) purposes. Jam STAPL is a freely
licensable open standard. It supports programming or configuration of programmable devices
and testing of electronic systems, using the IEEE 1149.1 Joint Test Action Group (JTAG)
interface. Device can be programmed or verified, but Jam STAPL does not generally allow
other functions such as reading a device.
The Jam STAPL programming solution consists of two components: Jam Composer and Jam
Player.
The Jam Composer is a program, generally written by a programmable logic vendor, that
generates a Jam file (.jam) containing the user data and programming algorithm required to
program a design into a device.
The Jam Player is a program that reads the Jam file and applies vectors for programming and
testing of devices in a JTAG chain.
The devices can be programmed in ZIF socket of the programmer or in target system through
ISP connector. It is indicated by [PLCC44](Jam) or (ISP-Jam) suffix after name of selected
device in control program. Multiple devices are possible to program and test via JTAG chain:
JTAG chain (ISP-Jam)
More information on the website:
www.altera.com
See please application notes:
"AN 425: Using the Jam Player to Program Altera Devices",
"AN 100: In-System Programmability Guidelines",
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