DFI LanParty UT NF590 SLI-M2R/G, Руководство пользователя

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BIOS Setup
Read to Write Delay (Trwt)
This field is used to select the read to write delay time. Although this
is not a DRAM specified timing parameter, it is related to the routing
latencies on the clock forwarded bus. This is measured from the first
address bus slot which is not associated with part of the read burst.
Write to Read Delay (Twtr)
This field is used to select the write to read delay time. This is
measured from the rising edge of the last non-masked data strobe
to the rising edge of the next read command.
Refresh Period Time (Tref)
This field is used to select the number of clock cycles between each
refresh.
Max Async Latency
This field is used to select the DRAM maximum asynchronous la-
tency time.
Bank Interleave
The options are Auto, Enabled and Disabled.
DRAM On-Die Termination
The options are Auto, Disabled, 075 ohm, 150 ohm, 050 ohm.
Read Delay From Rx FIFO
This field is used to select the delay from DQS receiving to first
data read from Rx FIFO. The options are Auto, 0.5 CLK, 1.0 CLK,
1.5 CLK, 2.0 CLK, 2.5 CLK, 3.0 CLK, 3.5 CLK and 4.0 CLK.
Read/Write Queue Bypass
This field is used to select the number of times the first operation in
the DCI read/write queue can be bypassed before the arbiter is
overridden and the first operation is chosen.