D
Data Structures and Memory Layout
This appendix contains definitions of the key global data structures used by
the CPU firmware.
D.1 Halt Dispatch State Machine
The CPU halt dispatcher determines what actions the firmware will take on
halt entry based on the machine state. The dispatcher is implemented as a
state machine, which uses a single bitmap control word and the transition (see
Table D–1) to process all halts. The transition table is sequentially searched
for matches with the current state and control word. If there is a match, a
transition occurs to the next state.
The control word comprises the following information:
•
Halt Type,
used for resolving external halts. Valid only if Halt Code is
00.
000 : power-up state
001 : halt in progress
010 : negation of Q22–bus DCOK
011 : console BREAK condition detected
100 : Q22–bus BHALT
101 : SGEC BOOT_L asserted (trigger boot)
•
Halt Code,
compressed form of SAVPSL<13:8>(RESTART_CODE).
00 : RESTART_CODE = 2, external halt
01 : RESTART_CODE = 3, power-up/reset
10 : RESTART_CODE = 6, halt instruction
11 : RESTART_CODE = any other, error halts
Data Structures and Memory Layout D–1
