System Initialization and Acceptance Testing (Normal Operation)
4.4 Basic Acceptance Test Procedure
Examine MEMCON 0–7 to verify the memory configuration. Each pair of
MEMCONs maps one MS690 memory module as follows:
MEMCON0–1
First MS690; slot 4, closest to CPU
MEMCON2–3
Second MS690; slot 3
MEMCON4–5
Third MS690; slot 2
MEMCON6–7
Fourth MS690; slot 1, farthest from CPU
Verify the following:
• The bank enable bit (<31>) in both MEMCONs for each memory
module is set to (8xxx xxxh), which indicates that the base address for
the banks contained on the module is valid.
• MEMCON bits <2:1> are the signature field and contain the following
value (Table 4–4), in relation to the size of the array.
Table 4–4 Signature Field Values
MCSR 0–15
<2:1>
Hex
Equiv
Configuration
00
0
Unassigned
01
2
RAM size 1 Mbit
10
4
RAM size 4 Mbits
11
6
Bank no response
• MEMCON bits <28:24> indicate the base address for each memory
bank. The first valid bank starts at 0. The memory subsystem can mix
the different sized memory modules (32 MB, 64 MB, and 128 MB). The
largest sized memory module will be configured first, no matter where
it is in the system. After all modules of the largest size are configured,
the next largest size will be configured.
• MEMCONs display 0000 0007 if no memory module is present; there
should be no gaps in the memory configuration.
3. Check the Q22–bus and the Q22–bus logic in the KA681/KA691/KA692
/KA694 CQBIC chip and the configuration of the Q22–bus, as follows:
System Initialization and Acceptance Testing (Normal Operation)
4–17
