SERVICE
34
MAGNET POWER SUPPLY SYSTEM 8500
4.2.4.
Parallel Communication:
The power supply can also be remotely controlled through a parallel interface also called CAMAC
interface. This requires mostly an additionally customer module attached to plug P3. E.g.
CAMAC/IGOR interface or equivalent.
Controlled by the CAMAC interface, serial status readings are still possible; but many of the
advanced features, as the first catch interlock register, Analog measurements or the real time clock,
are not aviable from the CAMAC port.
The parallel control consists of following TTL compatible lines.
- Control lines:
ON, OFF, RESET, INV polarity (Active high pulses)
- Current setting digital: 20 bit digital current set.
- Current setting Analog: Must be connected directly to the regulation module.
- Status lines Digital:
Interlocks and status
- Status lines Analog:
Actual current, Output voltage and Pass bank voltage if applicable.
- Water Flow measurement:
Please se P3 plug interface specifications for further signal information.
To activate the CAMAC interface must pin A32 be pulled low. This will turn the DAC setting
buffer’s IC24, IC26 and IC28 to inputs, and if set to remote operation will the FPGA IC20 reroute
the DAC setting bits to the regulation module. !!
Be aware
!! if A32 is left open, will the DAC
setting buffer’s be directed as outputs. This enables parallel operation of more tracking supplies,
where one acts as master and the other as inputs with CAMAC interface with P3.A32 pulled low.
The interlock status bits are always enabled as outputs IC25 and IC27.
IC28 is also used to pass the control signals ON, OFF, RESET, INVERT
.
4.2.5.
Interlock, status and OF/OFF control:
The interlock, status and ON/OFF signals are processed by this block. See page 2 of the diagram
83853.
External interlock and status signals are opto isolated from the electronics. The opto couplers are
driven from an isolated 24 Volt supply, with a current of 24 mA which ensures a good contact
cleaning.
Internal interlock and status signals are connected directly without galvanically isolation.
Inputs that are configured as interlock are hard wired (OR’ed) to the OFF circuit through diodes.
Soldered straps in series with the diodes decide if the signal has to be treated as interlock or status.
If the signal also has to latched and incorporated within the first catch register, can be programmed
with the “Esc”INTERLOCK command. Please see the SW appendix for further information on this.
DANFYSIK A/S - DK 2630 TAASTRUP - DENMARK.
DOC NO P80303Sk