Cypress S29CD016J, Руководство пользователя

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S29CD032J
S29CD016J
S29CL032J
S29CL016J
17.8 Erase and Programming Performance
Notes
84. Typical program and erase times assume the following conditions: 25°C, 2.5V V
CC
, 100K cycles. Additionally, programming typicals assume checkerboard pattern.
85. Under worst case conditions of 145°C, V
CC
= 2.5V, 1M cycles.
86. The typical chip programming time is considerably less than the maximum chip programming time listed.
87. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
88. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 34 and Table 35 for further
information on command definitions.
89. PPBs have a program/erase cycle endurance of 100 cycles.
90. Guaranteed cycles per sector is 100K minimum.
17.9 PQFP and Fortified BGA Pin Capacitance
Notes
91. Sampled, not 100% tested.
92. Test conditions T
A
= 25°C, f = 1.0 MHz.
Table 28. Erase and Programming Performance
Parameter Typ (Note 84) Max (Note 85) Unit Comments
Sector Erase Time 0.5 5 s
Excludes 00h programming prior to erasure
(Note 87)
Chip Erase Time
16 Mb = 23
32 Mb = 46
16 Mb = 230
32 Mb = 460
s
Double Word Program Time 8 130 µs
Excludes system level overhead (Note 88)
Accelerated Double Word Program Time 8 130 µs
Accelerated Chip Program Time
16 Mb = 5
32 Mb = 10
16 Mb = 50
32 Mb = 100
s
Chip Program Time, x32 (Note 86)
16 Mb = 12
32 Mb = 24
16 Mb = 120
32 Mb = 240
s
Table 29. PQFP and Fortified BGA Pin Capacitance
Parameter Symbol Parameter Description Test Setup Typ Max Unit
C
IN
Input Capacitance V
IN
= 0 6 7.5 pF
C
OUT
Output Capacitance V
OUT
= 0 8.5 12 pF
C
IN2
Control Pin Capacitance V
IN
= 0 7.5 9 pF