Cypress S29CD016J, Руководство пользователя

Страница: 43 / 74

Document Number: 002-00948 Rev. *C Page 43 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
8.6 Hardware Data Protection Methods
The device offers several methods of data protection by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describe these methods.
8.6.1 WP# Method
The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large bank.
If the system asserts V
IL
on the WP# pin, the device disables program and erase functions in the two “outermost” boot sectors (8-
Kbyte sectors) in the large bank. If the system asserts V
IH
on the WP# pin, the device reverts to whether the boot sectors were last
set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last
protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result.
The WP# pin must be held stable during a command sequence execution
8.6.2 Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The system must provide the proper signals to the control inputs to prevent
unintentional writes when V
CC
is greater than V
LKO
.
8.6.3 Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.6.4 Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power-up, the device does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to the read mode on power-up.
8.6.5 V
CC
and V
IO
Power-up And Power-down Sequencing
The device imposes no restrictions on V
CC
and V
IO
power-up or power-down sequencing. Asserting RESET# to V
IL
is required
during the entire V
CC
and V
IO
power sequence until the respective supplies reach the operating voltages. Once V
CC
and V
IO
attain
the operating voltages, deassertion of RESET# to V
IH
is permitted. Refer to timing in V
CC
and V
IO
Power-up on page 52 .
8.6.6 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
, or WE# = V
IH
. To initiate a write cycle, CE# and WE# must be
a logical zero (V
IL
) while OE# is a logical one (V
IH
).