Document Number: 002-00948 Rev. *C
S29CD032J
S29CD016J
S29CL032J
S29CL016J
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at
a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its
outputs to arrive asynchronously with the address on its inputs.
The internal state machine is set for asynchronously reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and
should be used for device selection (CE# must be set to V
IL
to read data). OE# is the output control and should be used to gate data
to the output pins if the device is selected (OE# must be set to V
IL
in order to read data). WE# should remain at V
IH
(when reading
data).
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable access time (t
CE
) is the
delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time (t
OE
) is the delay
from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least a period of t
ACC
-
t
OE
and CE# has been asserted for at least t
CE
-t
OE
shows the timing diagram of an asynchronous read operation.
Figure 1. Asynchronous Read Operation
Note
22.Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Refer to
Asynchronous Operations on page 52
for timing specifications and to
Figure 19 Conventional Read Operations Timings
for another timing diagram. I
CC1
in the DC Characteristics table represents the active current specification for reading
array data.
D0
D1
D2
D3
D3
CE#
CLK
ADV#
Addresses
Data
OE#
WE#
IND/WAIT#
V
IH
Float
V
OH
Address 0
Address 1
Address 2
Address 3
Float
