Document Number: 002-00948 Rev. *C
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Figure 4. Initial Burst Delay Control
Notes
32. Burst access starts with a rising CLK edge and when ADV# is active.
33. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
34. CR [13-10] = 1 or three clock cycles.
35. CR [13-10] = 2 or four clock cycles.
36. CR [13-10] = 3 or five clock cycles.
7.4.3 Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the
device defaults to the asynchronous read mode and the configuration register settings are in their default state. (See
for
the default Configuration Register settings.) The host system determines the proper settings for the entire configuration register, and
then execute the Set Configuration Register command sequence before attempting burst operations. The configuration register is
not reset after deasserting CE#.
The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the Configuration
Register commands. The Configuration Register is readable at any time, however, writing the Configuration Register is restricted to
times when the Embedded Algorithm™ is not active. If the user attempts to write the Configuration Register while the Embedded
Algorithm is active, the write operation is ignored and the contents of the Configuration Register remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation, DQ31–DQ16 returns all
zeroes. Also, the Configuration Register reads operate the same as the Autoselect command reads. When the command is issued,
the bank address is latched along with the command. Read operations to the bank that was specified during the Configuration
Register read command return Configuration Register contents. Read operations to the other bank return flash memory data. Either
bank address is permitted when writing the Configuration Register read command.
The configuration register can be read with a four-cycle command sequence. See
Command Definitions on page 67
for sequence
details.
CLK
ADV#
Addresses
DQ31-DQ0
3
DQ31-DQ0
4
DQ31-DQ0
5
Valid Address
Three CLK Delay
2nd CLK
3rd CLK
4th CLK
5th CLK
1st CLK
Four CLK Delay
Address 1 Latched
Five CLK Delay
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D3
D4
