Document Number: 002-00948 Rev. *C
S29CD032J
S29CD016J
S29CL032J
S29CL016J
7.6
VersatileI/O (V
IO
) Control
The VersatileI/O (V
IO
) control allows the host system to set the voltage levels that the device generates at its data outputs and the
voltages tolerated at its data inputs to the same voltage level that is asserted on the V
IO
pin. The output voltage generated on the
device is determined based on the V
IO
level. For the 2.6 V (CD-J), a V
IO
of 1.65 V–3.6 V (CD032J has a V
IO
of 1.65 V to 2.75 V)
allows the device to interface with I/Os lower than 2.5 V. For a 3.3 V V
CC
(CL-J), a V
IO
of 1.65 V–3.60 V allows the device to
interface with I/Os lower than 3.0 V.
7.7
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following
sections. However, prior to any programming and or erase operation, devices must be set up appropriately as outlined in the
configuration register (see
). During a synchronous write operation, to write a command or command sequence
(including programming data to the device and erasing sectors of memory), the system must drive ADV# and CE# to V
IL
, and OE# to
V
IH
when providing an address to the device, and drive WE# and CE# to V
IL
, and OE# to V
IH
when writing commands or
programming data.
7.7.1 Programming
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed
by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses
and verifies the programmed cell margin.
Command Definitions on page 67
shows the address and data requirements for the
program command sequence.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode and address are no longer latched. An
address change is required to begin reading valid array data.
The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. Refer to
for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data#
Polling algorithm to indicate the operation was successful. A succeeding read shows that the data is still “0.” Only erase operations
can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend
command.
A hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the
device has returned to the read mode, to ensure data integrity.
For the 32Mb S29CD-J and S29CL-J devices only:
Refer to the application note “
Recommended Mode of Operation for Cypress
®
110 nm S29CD032J/S29CL032J Flash Memory
”
publication number
S29CD-CL032J_Recommend_AN
for programming best practices.
