Cypress S29CD016J, Руководство пользователя

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Document Number: 002-00948 Rev. *C Page 54 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
17.3 Synchronous Operations
Notes
62. Using the max t
AAVS
and min t
ADVCS
specs together will result in incorrect data output.
63. Not 100% tested
64. Recommended 50% Duty Cycle
Table 24. Burst Mode for 32 Mb and 16 Mb
Parameter
Description
Speed Options
Unit
JEDEC Std.
75 MHz,
0R
66 MHz,
0P
56 MHz,
0M
40 MHz,
0J/1J
t
BACC
Burst Access Time Valid Clock to Output Delay
Max 8 8 8 8 ns
t
ADVCS
ADV# Setup Time to Rising Edge of CLK
Min 6 ns
t
ADVCH
ADV# Hold Time from Rising Edge of CLK
Min 1.5 ns
t
ADVP
ADV# Pulse Width
Min 7.5 8.5 9.5 10.5 ns
t
BDH
Valid Data Hold from CLK (Note 63)
16 Mb
Min 2 2 3 3 ns
32 Mb
Min 0 0 0 0 ns
t
INDS
CLK to Valid IND/WAIT# (Note 63)
Max 8 ns
t
INDH
IND/WAIT# Hold from CLK (Note 63)
Min 2 2 3 3 ns
t
IACC
CLK to Valid Data Out, Initial Burst Access
Max 48 54 54 54 ns
t
CLK
CLK Period
Min 13.3 15.15 17.85 25 ns
Max 60
t
CR
CLK Rise Time (Note 63)
Max 3 ns
t
CF
CLK Fall Time (Note 63)
Max 3 ns
t
CLKH
CLK High Time (Note 64)
Min 6.65 6.8 8.0 11.25 ns
t
CLKL
CLK Low Time (Note 64)
Min 6.65 6.8 8.0 11.25 ns
t
OE
Output Enable to Output Valid
Max 20 ns
t
DF
t
OEZ
Output Enable to Output High-Z (Note 63)
Min 2 2 3 3 ns
Max 7.5 10 15 17
t
EHQZ
t
CEZ
Chip Enable to Output High-Z (Note 63)
Max 7.5 10 15 17 ns
t
CES
CE# Setup Time to Clock
Min 4 4 5 6 ns
t
AAVS
ADV# Falling Edge to Address Valid (Note 62)
Max 6.5 ns
t
AAVH
Address Hold Time from Rising Edge of ADV#
Min 1
CLK
cycle
t
RSTZ
RESET# Low to Output High-Z (Note 63)
Max 7.5 10 15 17 ns
t
WADVH1
ADV# Falling Edge to WE# Falling Edge
Min 0 ns
t
WADVH2
ADV# Rising Edge to WE# Rising Edge
Min 10 ns
t
WADVS
WE# Rising Edge Setup to ADV# Falling Edge
Min 11.75 ns