CXR Larus 80-100-400
Issue 1, July 2006
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18
5.5224 (continued)
Before the clock card is stabilized, such as in the Free Run or Acquire 1 state,
the active clock will output a DUS ("Do not use") SSM. This is during initial
startup. After the startup period, the SSM described above will be generated
or passed through.
If a command is executed for SSM on the standby clock card, the SSM
message will be STU. In this case the message should be ignored.
5.5225 Power
An on-card power converter provides the necessary circuit voltages from the
diode-combined A and B -48 volt battery supplies. The on-card fuse, if it
blows, lights the red FAIL LED and provides battery to the Fuse Alarm bus
connecting to pin 10 on the backplane terminal strip TB1.
Nominal input is -57 Vdc to -42 Vdc. The power supply shuts off when the
input voltage rises goes past -38 Vdc and does not turn on again until the
supply attains -43 Vdc. The power supply is able to withstand transient
voltages down to -200 Vdc lasting less than 1 millisecond.
The 54522 su5 V at 2 amps, -5 V at 100 mA, +12 V at 500 mA, and
+15 V at 100 mA.
5.6 Model 54523 Stratum 2/TNC Track and Hold Clock Card
5.6010 There are two 54523 track and hold cards in a redundant Stratum 2/TNC
(Transit Node Clock) system. The 54523-3 supports the AB input architecture.
The AA input architecture is not supported (see Appendix A).
5.61 Functions
5.6110 The Model 54523 clock card performs the following functions:
a. Accepts one of two 1.544 MHz clock signals, extracts its timing, and
provides a smoothed and jitter free signal to the output cards from a
rubidium oscillator tracking the input reference.
b. Monitors reference input for framing and CRC errors. An
out-of-specification input signal forces the card to hold to the last known
reference, with a drift less than 7.5 x 10
-11
in 24 hours. By means of a
digital phase detector, the 54523 measures the input DS1/E1 reference bit
time phase compared to the rubidium atomic oscillator output as
conditioned by a DDFS. Samples of phase information are collected and
averaged over about a seven-second period to provide input to the control
algorithm. If, at any point in the accumulation and calculation period, a
condition is detected (excessive errors, LOS, OOF, etc.) which causes the
collected information to be suspect, the unit enters the holdover state and
does not update the correction to the synthesizer. If the data are qualified,
then the update will proceed. After 128 acquire cycles (about 15 minutes)
Содержание 54500-16
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