CXR 54500-16, Руководство пользователя

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The 54573 block diagram appears in Figure 5-14; the block diagram for the
54574 is shown in Figure 5-15.
5.1521 Clock Select Switch
The clock select switch is a 1.544 MHz clock selector with phase buildout
circuit, frame/byte synchronization system, LED indicators, and output
alarms. The selector output goes to a phase buildout circuit whose function
is to smooth out sudden phase changes (which might be as much as ±1/2 a
unit interval) occurring when the clock selection is changed. The change of
phase rate is limited to under 81 nanoseconds in 1.326 milliseconds.
5.1522
8.192 MHz PLL
An 8.192 MHz PLL produces a 2.048 MHz clock which is phase locked to
the 1.544 MHz clock selected at the input. The 54574 card converts the
2.048 MHz clock to a square wave and feeds it to the output drivers.
5.1523
E1 Transmit Framer
The E1 framer is produced inside the field programmable gate array (FPGA)
and frame synchronized from the external synchronization bus.