Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-12 VME6U HARDWARE REFERENCE
The host issues a WRITE to SCRAMNet
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shared memory. If Override TIE CSR0[9] or
ACR TIE ACR[1] is set and Network Interrupt Enable CSR0[8] is set, then the interrupt
message is transmitted (INT = 1). Otherwise, the message is transmitted without the
interrupt bit set (INT = 0). (See Table 5-1, page 5-4)
Network data WRITE interrupts can be accomplished by two methods:
•
Forced
. Any data WRITEs to any shared memory from the network will
generate an interrupt.
•
Masked or Selected.
Data writes to selected shared-memory locations from the
network. Under either of these two methods, an interrupt can be generated and
received by the same host processor if desired. This condition is called Self-
Interrupt.
FORCED INTERRUPT
The forced interrupt method works the same as the selected interrupt method with the
exception of choice of interrupt locations. All shared-memory locations are automatically
set up to receive and/or transmit interrupts depending upon the override bits set in CSR0
or CSR8.
MASKED OR SELECTED INTERRUPT
The masked or selected interrupt method requires choosing SCRAMNet
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shared-
memory locations on each node to receive and/or transmit interrupts. These shared-
memory locations may also be used to generate signals to external triggers. The
procedure for selecting shared-memory locations for interrupts and/or external triggers is
explained in paragraph 5.6: Auxiliary Control RAM.
CSR5 contains the Interrupt FIFO Not Empty bit CSR5[15].
SELF-INTERRUPT
Set CSR2[10:9] to enable self-interrupt. This allows the message with the interrupt bit set
to be processed as an incoming network interrupt. CSR2[9] enables the node’s own
message to be received as a network message. CSR2[10] allows the interrupt bit to
generate an interrupt if it is set.
Receive Interrupt logic is described in Figure 5-3. If a native message is received and
Write Own Slot CSR2[9] is enabled, and Enable Interrupt on Receipt in own Slot
CSR2[10] is set, the logic then checks for Receive Interrupt Enable. If Override RIE
CSR0[6] is set or ACR RIE ACR[0] is set, and if Interrupt Mask Match Enable is set, the
address is placed on the Interrupt FIFO.
NOTE
: Interrupt data is not filtered when the data filter is enabled