Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-15 VME6U HARDWARE REFERENCE
5.8.3 Interrupt Handling
The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant
seven bits of the 23-bit SCRAMNet
+
interrupt address and CSR4 contains the remaining
16 bits of the interrupt address. (The 23-bit address allows for future expansion of
memory). CSR5 also contains Interrupt FIFO Not Empty (bit 15).
NOTE
: The SCRAMNet
+
Network is a longword (32-bit)-oriented shared memory.
External Triggers and Interrupts will occur when any of the four bytes associated with a
long word are accessed. The Interrupt FIFO contains the longword address. If each of
the four bytes of an interrupt location are written into as byte accesses, then four
interrupts to the same longword address will be generated. Likewise, if each word of an
interrupt location is written into as 16-bit shortwords, then two interrupts to the same
longword address will be generated.
The two values of CSR5 and CSR4 make up the interrupt address. When an interrupt is
received, the ISR should READ CSR5 first in order to check the Interrupt FIFO Not
Empty bit. If this bit is set (value is ‘1’), then READ CSR4. If this bit is CLEAR (value is
0) then the Interrupt FIFO is empty. Therefore, the interrupt was due to an error,
assuming that Enable Interrupt On Error is set.
Every READ from CSR5 and CSR4 will contain the SCRAMNet
+
memory address of
the data received from the network interrupt. Every READ of CSR5 and CSR4 will
automatically increment the FIFO pointer to the next interrupt address for both registers.
CSR4 should be read only if Interrupt FIFO Not Empty CSR5[15] is set. Continue to
READ CSR5 and CSR4 until the Interrupt FIFO Not Empty bit is zero. Writing any value
to CSR1 will re-enable interrupts. See Page 5-29 for an example of a standard ISR
algorithm for handling interrupts from the SCRAMNet
+
boards.
WARNING
: If HIPRO is enabled, an interrupt may affect the sequence of addresses on
a READ/WRITE if SCRAMNet
+
is manipulated in the ISR.
If an interrupt occurs before the interrupts have been armed, it will be placed in the
Interrupt FIFO and will occur when the interrupts are armed (CSR 1).
5.9 External Triggers
Two external triggers are provided by the SCRAMNet
+
Network. The external triggers
will occur only if the ACR has been configured to enable them. Triggers 1 and 2 are
generated by SCRAMNet
+
shared-memory access. Triggers generate a 26.64 ns TTL
level compatible, non-terminated, output.
•
Trigger 1 - Host READ/WRITE (ACR[2] enables)
•
Trigger 2 - Network WRITE (ACR[3] enables)
Trigger 1 will be generated for any host access to SCRAMNet
+
memory.
Trigger 2 will be generated by a network WRITE to the SCRAMNet
+
memory.
The trigger output signals are available through the external trigger connection pins, if
installed on the board. Also, pin 7 of the Auxiliary Connector is connected to TRIG1.
The triggers can be used to measure time intervals or to start or stop an external event.