Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-16 VME6U HARDWARE REFERENCE
EXAMPLE 1 – MEASURE TRANSACTION TIME
Select a shared-memory address in node A and enable trigger 1 by setting ACR[2]. Select
the same memory address in node B and enable trigger 2 by setting ACR[3]. Connect a
wire from TRIG1 to an oscilloscope. Connect a wire from TRIG2 to the oscilloscope.
Initiate a HOST WRITE to the node A memory address. When the corresponding
NETWORK WRITE occurs, the time difference can be measured.
EXAMPLE 2 – MEASURE RING TIME
Enable WRITE-ME-LAST mode on node A. Select a shared memory address and enable
trigger 1 and trigger 2 for that address. Connect a wire from TRIG (pin 3 - trigger 1 OR
2) to an oscilloscope. Initiate a HOST WRITE to that memory address. The time
difference displayed on the oscilloscope will approximate the ring time—the time it takes
from the HOST WRITE on node A to the NETWORK WRITE on node A.
EXAMPLE 3 – SET OFF AN ALARM
Enable trigger 1 for the shared memory address of a critical datum by setting ACR[2].
Connect a wire from TRIG1 to an alarm light. When the HOST WRITE to that memory
address occurs, the light will come on.
5.10 General Purpose Counter/Timer
This 16-bit counter/timer can be programmed by changing CSR9[13] and CSR9[14] to
select the desired mode as described in Table 5-5. CSR8[9] can be set to override the
counter/timer mode settings and allow the counter/timer to run free at 26.66 ns
(37.5 MHz). CSR9[12] can be set to generate an interrupt upon overflow of the
counter/timer. The output from the event counter/timer is stored in CSR13. See Appendix
B, pages B-6, B-12, and B-14 for more information.
5.10.1 Available Modes
The General Purpose Counter/Timer register (CSR13) can be used as a counter or a
timer. The mode is selected via a combination of registers and bits that are explained on
page 5-13. Table 5-5 describes the counter/timer modes available:
Table 5-5 General Purpose Counter/Timer Modes
Mode Description
Count Errors: Each error detected in CSR1 will increment the counter by 1.
Count Trigger 1 and 2: Each time a trigger event occurs the counter will increment.
Transit Time: Set this mode and clear the counter. The counter will begin
counting when the next message is transmitted, and stop
counting when any message generated by this node is
received.
Network Events: Count incoming network messages.
Free Run @ 26.66 ns: Increment counter using internal 37.5 MHz clock. Counter will
roll over every 1.78 ms.
Free Run @ 1.706
μ
s
with Trigger 2 to CLEAR:
Increment counter using the 585.9 KHz clock. Counter will roll
over every 111.8 ms. Assertion of Trigger 2 will clear the
counter.