SCRAMNET NETWORK
Copyright 2007
2-10
VME6U HARDWARE REFERENCE
2.10.2 High Performance (HIPRO) Mode
HIPRO provides an efficient means to transmit 8-bit and 16-bit data transactions as one
32-bit network WRITE. It also provides a means of keeping 32-bit data from becoming
fractured.
EXAMPLE #1:
A floating-point length numeric sent in 8-bit or 16-bit pieces may not be accurately re-
assembled at the destination.
EXAMPLE #2:
The receiving node may otherwise try to use part or half of such a value before the entire
32 bits is received.
HIPRO WRITE
The SCRAMNet
+
network message is based on 32-bit longword data. This means if any
8-bit field of the 32-bit buffer is changed, the entire 32-bit message is transmitted. If a
host is limited to only 8-bit or 16-bit databus transactions the network throughput is
quartered or halved, respectively.
HIPRO mode permits a 32-bit location to be set up in shared memory such that any initial
WRITE smaller than 32 bits to that location will not automatically go onto the network.
The 32-bit WRITE to the network will only occur when all four bytes within the 32-bit
location have been written through subsequent WRITEs by the host CPU. This can be
accomplished by four consecutive 8-bit or two consecutive 16-bit WRITEs to the
SCRAMNet
memory.
NOTE
: HIPRO WRITE will not work if Disable Host to Memory Write CSR2[8] is set,
or when writing two separate shortwords while using interrupts.
HIPRO READ
The HIPRO READ is controlled by CSR16. This register is CSR enabled and ACR
location selectable.
To conserve host cycles and increase host throughput, HIPRO READ mode allows the
host to get part of the information (1 shortword or 2 bytes) during the first READ on that
longword boundary. On the next READ operation (not the same location or within the
same longword boundary) the remaining data is provided.
2.10.3 VME Holdoff Mode
It is possible that the Transmit FIFO can become full when the host is writing to the
SCRAMNet
+
interface faster than the network can absorb the data.
In VME Holdoff mode, the host WRITE cycle is automatically extended until the
SCRAMNet
+
Transmit FIFO buffer transmits at least one message. This prevents the loss
of data and is transparent to the user.
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