Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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SCRAMNET NETWORK
Copyright 2007 2-6 VME6U HARDWARE REFERENCE
2.6.1 Network Interrupt WRITEs
FOREIGN MESSAGE
The node can receive a message from another node with the interrupt bit set. If Receive
Interrupt Enable ACR[0] and Interrupt Mask Match Enable CSR0[5] are enabled, the
data is written to shared memory and the address is placed on the Interrupt FIFO.
NATIVE MESSAGE
If the message received was originated by the node, and Write Own Slot Enable CSR2[9]
and Enable Interrupt on Own Slot CSR2[10] are enabled, the host has authorized a Self-
Interrupt. The data is written to shared memory and the address is placed on the Interrupt
FIFO.
Network Interrupt WRITEs can be accomplished by two methods:
•
Selected
. Data WRITEs to selected shared memory locations from the network.
•
Forced
. Any data WRITEs to any shared memory from the network.
In either case, the node can be configured to WRITE to itself. This condition is called
“Self Interrupt.”
2.6.2 Selected Interrupt
The selected-interrupt method requires choosing SCRAMNet
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shared-memory locations
on each node to receive and/or to transmit interrupts. These shared-memory locations
may also be used to generate signals to external triggers. The procedure for selecting
shared-memory locations for interrupts and/or external triggers is explained in the
paragraph on the Auxiliary Control RAM, paragraph 2.5.
OUTGOING INTERRUPT
The Outgoing Interrupt is described in Figure 2-3. If both Transmit Interrupt Enable
ACR[1] and Network Interrupt Enable CSR0[8] are set, and a data item is transmitted to
any of the selected-interrupt memory locations, then an interrupt message is sent out on
the network. This message will generate interrupts to any processors on the network that
have that same shared-memory location selected to receive interrupts.
INCOMING INTERRUPT
Figure 2-4 demonstrates the process of receiving a message with the interrupt bit set. The
data is written to shared memory and the address is placed in CSR5 and CSR4 to await
being sent to the host. If the Receive Interrupt Enable ACR[0], Host Interrupt Enable
CSR0[3], and the Interrupt Memory Mask Match Enable CSR0[5] are set, and network
interrupt data is received for any one of the selected-interrupt memory locations
the following occurs:
•
The data is stored in that location
•
The SCRAMNet
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address of the memory location is placed on the Interrupt
FIFO queue, and
•
An interrupt is sent to the processor.