Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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SCRAMNET NETWORK
Copyright 2007 2-5 VME6U HARDWARE REFERENCE
0
1
Shared Memory
ACR Memory
CSR0[4]
Host READ/WRITE
request to a specific
32-bit memory address
Byte 0 Byte 1 Byte 2 Byte 3
Byte 0
PHYSICAL
MEMORY CHIP
DOES NOT
REALLY EXIST
LEGEND
Figure 2-2 ACR/Memory Access
In
Figure 2-2
, host CPU READ/WRITE operations are channeled to either SCRAMNet
+
memory or to the ACR. The ACR is a physically separate memory from the shared
memory. Channeling is based on a user-controlled switch setting and may be toggled to
the desired position by writing to a bit in the SCRAMNet
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CSR. When access to the
ACR is enabled, shared memory is not accessible by the host and the ACR byte is viewed
as the least significant byte (LSB) of every shared-memory four-byte address. The ACR
bits define what external trigger and/or interrupt action(s) are to be taken whenever
writing to any byte of the SCRAMNet
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shared memory 4-byte word.
Only five bits of the ACR are associated with every four-byte word of shared memory
(on even four-byte boundaries). The other 27 bits of the ACR are phantom bits and do not
physically exist.
2.6 Interrupts
SCRAMNet
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allows a node processor to receive interrupts from and transmit interrupts
to any node on the network, including the originating node, provided the receiving node
is set up to receive an interrupt message. Interrupts can be generated under two different
conditions:
•
SCRAMNet
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Network data WRITEs to shared memory; and
•
SCRAMNet
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network errors detected on the local node.
SCRAMNet
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interrupts usually require a device driver to interface with the node
processor. There must also be a host-dependent interrupt vector placed in CSR6 and
CSR7 identifying the Interrupt Service Routine (ISR). The driver is required primarily to
permit the host processor to handle interrupts from the SCRAMNet device.