CSR DESCRIPTIONS
Copyright 2007
B-10
VME6U HARDWARE REFERENCE
Table B-7 CSR6
Bits
Interrupt Vector (Memory Update)
(READ/WRITE)
7-0
Interrupt Vector -
This host specific register stores the VMEbus interrupt vector for the
interrupt generated by a Memory Update. This register must be pre-loaded with the vector
before interrupt processing can occur. *
15-8 Reserved.
Table B-8 CSR7
Bits
Interrupt Vector (S Error)
(READ/WRITE)
7-0
Interrupt Vector -
This host specific register stores the VMEbus interrupt vector for the
interrupt generated by a SCRAMNet
+
Error. This register must be pre-loaded with the vector
before interrupt processing can occur. *
15-8 Reserved.
*
Both Interrupt Vectors are tied to the same Interrupt Request (IRQ) level set in CSR15
Содержание SCRAMNet+ SC150 VME6U
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