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FPDP PRIMER
Copyright 2017 9-6 FibreXtreme Hardware Reference
9.5
Parallel FPDP Signal Timing
Figure 9-2 shows the timing for several FPDP interface signals. This figure is accurate for
all four data framing types. See section 9.3.2 for a discussion of framing. The Data Valid
signal, /DVALID, is asserted by the FPDP-TM when valid data is transmitted onto the
FPDP bus but not before at least 16 STROBE periods have occurred. The FPDP-TM must
de-assert /DVALID when no more data remains in its buffer until valid data is again
available. To avoid losing data when the receiver’s FIFO is almost full, the receiver
(FPDP-RM or FPDP-R) must assert the /SUSPEND signal to hold off the transmitter. The
FPDP-TM must de-assert /DVALID within 16 STROBE periods and keep it de-asserted
until /SUSPEND is de-asserted. Per the FPDP specification, after /SUSPEND is de-
asserted, the FPDP-TM must wait for at least one STROBE period before re-asserting
/DVALID. With the FibreXtreme SL240 card, after /SUSPEND is de-asserted, the FPDP-
TM must wait for at least two STROBE periods before re-asserting /DVALID. The
/SUSPEND signal is asynchronous to the STROBE clock and should be double
synchronized by the FPDP-TM before being used in order to avoid metastability
problems.
The FPDP-TM must not transmit data onto the FPDP bus until the Not Ready signal,
/NRDY, is de-asserted by the FPDP-RM and FPDP-R devices. The FPDP-RM and FPDP-
R devices must assert /NRDY when they are not ready to accept data and must de-assert
/NRDY otherwise. The /NRDY signal is asynchronous to the STROBE clock and should
be double synchronized by the FPDP-TM before being used in order to avoid metastability
problems.
As required by the
Front Panel Data Port Specifications, ANSI/VITA 17-1998,
the FPDP-
TM transmits the Data Direction signal /DIR.FPDP-RM and FPDP-R devices may receive
/DIR. The /DIR signal is not given a firm definition of use. Possible uses of this signal
include providing a status indication available to be read by software or to allow operation
to be inhibited until /DIR is asserted. The /DIR signal may be asynchronous with other
FPDP signals. An SL240 FPDP-R or FPDP-RM inverts and passes this signal from the
FPDP interface to the link interface. DIR is an active-high signal on the link interface.
/DIR is an active-low signal on the FPDP interface.
Two user-defined Programmable I/O (PIO) signals, PIO1 and PIO2, are reserved in the
Front Panel Data Port Specifications
. These are auxiliary signals that are not required for
core FPDP functions. However, these signals can be user-defined to allow the FPDP-TM,
FPDP-RM, and FPDP-R devices to transfer information that is not part of the FPDP
specifications. The FPDP-TM, FPDP-RM, and FPDP-R devices must not drive either of
the PIO lines immediately at power up of the system. This is to avoid the possibility of
two devices driving the same PIO line simultaneously and causing damage to the driver
device.