Curtiss-Wright FHF5-PC4MWB04-00, Справочник по аппаратуре

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FPDP PRIMER
Copyright 2017 9-3 FibreXtreme Hardware Reference
Some additional advantages of parallel FPDP are:
 Low cost, 32-bit parallel interface provided through a ribbon cable.
 160 MBps sustained data rate.
Some additional advantages of Serial FPDP are:
 Noise immune fiber-optic interface.
 Significantly increased transmission distance (10 km).
 Standard cards for parallel FPDP, custom backplanes, PCI (PCI/CPCI/PMC), and
others available.
9.2
Terminology
Some FPDP specific terms are defined below.
FPDP TRANSMIT MASTER (FPDP-TM)
An FPDP-TM is a device that transmits data and timing signals onto the FPDP bus. This
device also terminates the bus signals at one end of the ribbon cable bus for parallel FPDP.
Only one FPDP-TM may exist on an FPDP bus.
FPDP RECEIVE MASTER (FPDP-RM)
An FPDP-RM is a device that receives data from the FPDP bus synchronously with the
timing signals provided by the FPDP-TM. This device also terminates the bus signals at
one end of the ribbon cable bus for parallel FPDP. Only one FPDP-RM may exist on an
FPDP bus.
FPDP RECEIVER (FPDP-R)
An FPDP-R is a device that receives data from the FPDP bus synchronously with the
timing signals provided by the FPDP-TM. As opposed to the FPDP-RM, this device does
not terminate any bus signals on parallel FPDP. Multiple FPDP-R devices may exist on an
FPDP bus.
9.3
Parallel FPDP Theory of Operation
9.3.1 Clock Signals
A single FPDP-TM generates a free-running clock. This clock frequency determines the
maximum transfer rate on the bus. FPDP provides both a PECL (Positive Emitter Coupled
Logic) and TTL strobe on the bus, with the PECL clock used for higher frequency (> 20
MHz) transfers. If designing to the CMC card, only an LVTTL clock is generated by the
card’s FPDP transmitter port, since it is driving to a PCB instead of a long ribbon cable.
An FPDP receiver card (FPDP-R or FPDP-RM) accepts the PECL or TTL clock generated
by the transmitter and uses it as the word clock for the data transfers. This clock is
generally in the range of 0 to 40 MHz on standard FPDP busses, though the FPDP
specification does not state a hard maximum frequency at which the bus may be run. The
CMC card has a LVTTL clock input that it uses for the word clock.