Curtiss-Wright FHF5-PC4MWB04-00, Справочник по аппаратуре

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Copyright 2017 4-1 FibreXtreme Hardware Reference
4.
OPERATION
4.1
Overview
SL100/SL240 cards move data with very low latency between a host interface and a
1.0625 Gbps or a 2.5 Gbps link, respectively. The host interfaces available are an FPDP-
like proprietary interface and a PCI interface. The advantage of the FPDP-like interface is
that it requires very simplistic hardware to interface. The PCI interface will interface with
any standard PCI bus, and therefore has many advantages for portability at the cost of
some software overhead.
NOTE
: It is not possible for SL100 and SL240 cards to communicate/operate with one
another on the link because the link speeds are not compatible.
CAUTION
: Do
not
break the link between two SL100/SL240 cards. The
unpredictable results may affect your system. While the FPGA can recover from link
break scenarios, the corresponding link and data errors caused by disruption of the link
must be adequately addressed by the host interface.
4.2
Theory of Operation
The operation of SL240 cards is simple—take data from the host bus interface and
transmit it across a link, or take data from the link and pass it to the host bus interface.
The link protocol involved is kept minimal to reduce the latency and improve throughput,
while still providing a set of useful features with which to customize your applications.
The hardware offers many different features for advanced applications, while maintaining
a simple interface to the most commonly used features.
NOTE: For further explanation of terms used in this chapter, refer to the FPDP Primer
in Appendix E.
4.2.1 Receive Operation
The SL240 card has several options for receiving data. The most basic option is no-loop
operation with data-receive enabled. In this case, data is:
1. Received from the link.
2. Decoded by the card.
3. Placed in the receive FIFO.
At this point, the operation depends on the host interface.
If it is a PCI-based card and a receive DMA is started, the data is automatically moved
into the PCI address given by the DMA transaction. If no DMA is started, the data waits
in the receive FIFO until the host either PIOs the data out or sets up the DMA transaction
to remove it.
If it is an FPDP-based card, and /SUSPEND is not asserted, the card asserts /DVALID
and proceeds to transmit the data on the FPDP interface. If /SUSPEND or /NRDY is
asserted, then the data waits in the receive FIFO until these signals go away.