Curtiss-Wright FHF5-PC4MWB04-00, Справочник по аппаратуре

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REGISTERS
Copyright 2017 6-7 FibreXtreme Hardware Reference
Field Description Access Reset
Value
chain should have this bit set to '0.' Do not set this bit
to '1' on any device in a point-to-point topology (i.e. two
cards) because throughput will decrease by a factor
related to frame size. This bit was introduced in the
revision 0x1C.13 firmware.
13 Reserved None 0
14 Send IDLE
– Set to ‘1’ to send IDLE characters when
no data is being sent. Set to ‘0’ to send empty frames
when no data is being sent.
W 0
15 Reserved None 0
16 Reset SR
– Write ‘1’ to clear any latched status
information from the registers. Writing ‘0’ has no effect.
W 0
17 Clear SYNC without DVALID
– Write ‘1’ to release a
FIFO
stopped on SYNC without DVALID. Writing ‘0’
has no effect.
W 0
18 Clear Receiver Error
– Write ‘1’ to release a FIFO
stopped on a receiver error condition
. Writing ‘0’ has no
effect.
W 0
19 Erase TX FIFO
– Set to ‘1’ to reset the Transmit FIFO.
This bit is included for testing and special scenarios,
and as such, should not be used in the majority of
applications. Resetting the Transmit FIFO or Receive
FIFO independently from the SL100/SL240 FPGA logic
can cause undesirable effects because each 32-bit
Serial FPDP data word occupies two entries in the
respective FIFO and the link and host are
independently filling and draining these FIFOs.
Applying the FIFO resets without applying special
precaution can result in a misalignment of data in these
FIFOs.
W 0
20 Erase RX FIFO
– Set to ‘1’ to reset the Receive FIFO.
This bit is included for testing and special scenarios,
and as such, should not be used in the majority of
applications. Resetting the Transmit FIFO or Receive
FIFO independently from the SL100/SL240 FPGA logic
can cause undesirable effects because each 32-bit
Serial FPDP data word occupies two entries in the
respective FIFO and the link and host are
independently filling and draining these FIFOs.
Applying the FIFO resets without applying special
precaution can result in a misalignment of data in these
FIFOs.
W 0
31 to 21 Reserved None 0