Curtiss-Wright FHF5-PC4MWB04-00, Справочник по аппаратуре

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REGISTERS
Copyright 2017 6-1 FibreXtreme Hardware Reference
6.1
Overview
NOTE : The FibreXtreme SL100 and SL240 PCI and PMC Cards will be referred to
throughout this appendix as PCI. Anything that is exclusive to the PCI or PMC Cards
will be described as such.
The PCI SL240 card is very easy to program. With minimal programming, the PCI SL240
card can transfer data between PCI hosts. This section details the actual bit definitions to the
registers, which are explained in Appendix C (SL100/SL240 Programming).
NOTE : In some cases, the Receive FIFO Threshold register shows data in the FIFO, but
attempts to clear that data by reading from the FIFO fail.
6.2
Accessible resources
There are three accessible resources on the PCI SL240 card—PCI Configuration registers,
the runtime register set, and the FIFO. The mechanisms for accessing these are platform
specific and therefore outside the scope of this document, though the contents are detailed
here.
6.3
PCI Configuration registers
The PCI SL240 card contains a standard PCI configuration space header, with the device ID
of 0x4640 and the vendor ID of 0x1387. There are also two base addresses initialized for the
card – the first is a 256 byte space representing the runtime registers, the second is a one-
megabyte space reserved for the FIFO.
6.4
Runtime Register set
The runtime register set is accessed through 32-bit memory accesses to the Base Address 0
from PCI Configuration space. These registers represent all the configuration, control, and
status registers for the PCI SL240 card. Table B-1 shows the layout of these registers in PCI
space.
6.4.1 Bit Definitions
 R/W – Readable/Writable bit
 R/WOC – Readable/Write One to Clear bit

W –
Write-only bit

R –
Read-only bit