GR740-UM-DS, Nov 2017, Version 1.7
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After system reset, only the first processor will start (note that this depends on the value of the exter-
nal signal BREAK. If BREAK is high after system reset. The first processor will either be halted or go
into debug mode, depending on the value of external signal DSU_EN. All other processors will
remain halted in power-down mode.
After the system has been initialized, the remaining processors can be started by writing to the MP
status register, located in the multi-processor interrupt controller. The halted processors start execuing
from the reset address. Note that if the reset start address is changed (via the interrupt controller) then
the processors must be started via the interrupt controller’s Processor boot register.
6.3
Cache system
6.3.1
Overview
The LEON4 processor pipeline implements a Harvard architecture with separate instruction and data
buses, connected to two separate cache controllers. As long as the execution does not cause a cache
miss, the cache controllers can serve one beat of an instruction fetch and one data load/store per cycle,
keeping the pipeline running at full speed.
On cache miss, the cache controller will assert a hold signal freezing the IU pipeline, and after deliv-
ering the data the hold signal is again lifted so execution continues. For accessing the bus, the cache
controllers share the same AHB connection to the on-chip bus. Certain parts of the MMU (table walk
logic) are also shared between the two caches.
Another important component included in the data cache is the write buffer, allowing stores to pro-
ceed in parallel to executing instructions.
Cachability (memory areas that are cachable) for both caches is described in section 6.7.2.
6.3.2
Cache operation
Each cache controller has two main memory blocks, the tag memory and the data memory. At each
address in the tag memory, a number of cache entries, ways, are stored for a certain set of possible
memory addresses. The data memory stores the data for the corresponding ways.
For each way, the tag memory contains the following information:
•
Valid bits saying if the entry contains valid data or is free. Both caches have a single valid bit for
each cache line.
•
The tag, all bits of the cached memory address that are not implied by the set
•
If MMU is enabled, the context ID of the cache entry
•
Check bits for detecting errors
When a read from cache is performed, the tags and data for all cache ways of the corresponding set
are read out in parallel, the tags and valid bits are compared to the desired address and the matching
way is selected. In the hit case, this is all done in the same cycle to support the full execution rate of
the processor.
In the miss case, the cache will at first deliver incorrect data. However on the following cycle, a hold
signal will be asserted to prevent the processor from proceeding with that data. After the miss has
been processed, the correct data is injected into the pipeline using a memory data strobe (mds) signal,
and afterwards the hold signal can be released. If the missed address is cacheable, then the data read in
from the cache miss will be stored into the cache, possibly replacing one of the existing ways.
In the instruction streaming case, the processor pipeline is stepped one step for every received instruc-
tion. If the processor needs extra pipeline cycles to stretch a multi-cycle instruction or due to an inter-
lock condition (see section 6.2), or if the processor jumps/branches away, then the instruction cache
will hold the pipe, fetch the remainder of the cache line, and the pipeline will then proceed normally.
