GR740-UM-DS, Nov 2017, Version 1.7
173
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GR740
Table 160.
0x20,0x40,0x60,0x80 - RTR.AMBADMACTRL - AMBA port DMA control/status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INTNUM
RES
EP TR IE IT RP TP
RES
SP SA EN NS RD RX AT RA TA PR PS AI RI TI RE TE
0x00
0x0
0
0
0
0
0
0
0x0
0
0
0
0
0
0
0
0
0
0
0 NR NR NR 0
0
rw
r
wc wc rw rw wc wc
r
rw rw rw rw rw
r
rw wc wc wc wc rw rw rw rw rw
31: 26
Interrupt number (INTNUM) - The interrupt number used for this DMA channel when sending a distributed
interrupt code that was generated due to any of the events maskable by the RTR.AMBADMACTRL.IE and
RTR.AMBADMACTRL.IT bits. The value in this field should be in the range 0 to 31.
25: 24
RESERVED
23
EEP termination (EP) - Set to 1 when a received packet for the corresponding DMA channel ended with an
Error End of Packet (EEP) character.
22
Truncated (TR) - Set to 1 when a received packet for the corresponding DMA channel is truncated due to a
maximum length violation.
21
Interrupt transmit enable on EEP (IE) - When set to 1, the distributed interrupt code specified in the
RTR.AMBADMACTRL.INTNUM field is generated when a received packet on this DMA channel ended
with an Error End of Packet (EEP) character.
20
Interrupt-code transmit enable on truncation (IT) - When set to 1, the distributed interrupt code specified in
the RTR.AMBADMACTRL.INTNUM field is generated when a received packet on this DMA channel is
truncated due to a maximum length violation.
19
Receive packet IRQ (RP) - This bit is set to 1 when an AMBA interrupt was generated due to the fact that a
packet was received for the corresponding DMA channel.
18
Transmit packet IRQ (TP) - This bit is set to 1 when an AMBA interrupt was generated due to the fact that a
packet was transmitted for the corresponding DMA channel.
17: 16
RESERVED
15
Strip pid (SP) - Remove the pid byte (second byte) of each packet. The address byte (first byte) will also be
removed when this bit is set independent of the SA bit.
14
Strip addr (SA) - Remove the addr byte (first byte) of each packet.
13
Enable addr (EN) - Enable separate node address for this channel.
12
No spill (NS) - If cleared, packets will be discarded when a packet is arriving and there are no active descrip-
tors. If set, the GRSPW will wait for a descriptor to be activated.
11
Rx descriptors available (RD) - Set to one, to indicate to the GRSPW that there are enabled descriptors in the
descriptor table. Cleared by the GRSPW when it encounters a disabled descriptor:
10
RX active (RX) - Is set to ‘1’ if a reception to the DMA channel is currently active otherwise it is ‘0’.
9
Abort TX (AT) - Set to one to abort the currently transmitting packet and disable transmissions. If no trans-
mission is active the only effect is to disable transmissions. Self clearing.
8
RX AHB error (RA) - An error response was detected on the AHB bus while this receive DMA channel was
accessing the bus.
7
TX AHB error (TA) - An error response was detected on the AHB bus while this transmit DMA channel was
accessing the bus.
6
Packet received (PR) - This bit is set each time a packet has been received. never cleared by the SW-node.
5
Packet sent (PS) - This bit is set each time a packet has been sent. Never cleared by the SW-node.
4
AHB error interrupt (AI) - If set, an interrupt will be generated each time an AHB error occurs when this
DMA channel is accessing the bus.
3
Receive interrupt (RI) - If set, an interrupt will be generated each time a packet has been received. This hap-
pens both if the packet is terminated by an EEP or EOP.
2
Transmit interrupt (TI) - If set, an interrupt will be generated each time a packet is transmitted. The interrupt
is generated regardless of whether the transmission was successful or not.
1
Receiver enable (RE) - Set to one when packets are allowed to be received to this channel.
0
Transmitter enable (TE) - Write a one to this bit each time new descriptors are activated in the table. Writing
a one will cause the SW-node to read a new descriptor and try to transmit the packet it points to. This bit is
automatically cleared when the SW-node encounters a descriptor which is disabled.