DESCRIPTION AND OPERATION
CLOCK AND TIMER
2 - 2
I-E96-202B
®
circuit issues a board-wide reset and the status LED turns red.
This condition is known as a fatal error.
CLOCK AND TIMER
The clock section provides the clock signals that drive the mod-
ule at 16 megahertz. Additionally, this section supplies the
lower order clock signals for the on-board serial links, and the
system timer for uniform control algorithm execution. All clock
signals originate from either the 32 megahertz or 7.3728 mega-
hertz oscillators on the multi-function processor module.
The timer section keeps the multi-function processor module
task scheduling at the proper intervals. One of the UART
devices used for serial communication contains the timer
section.
MEMORY
The MFP module contains 512 kilobytes of ROM memory, 512
kilobytes of random access memory (RAM) and 256 kilobytes of
nonvolatile random access memory (NVRAM). It is important to
remember that only 347,712 bytes of RAM memory and
194,752 bytes of NVRAM memory are available for user config-
urations. The ROM memory holds the operating system
instructions for the microprocessor. The RAM memory pro-
vides temporary storage and a copy of the module configura-
tion. The NVRAM memory holds the module configuration
(control strategy designed with function codes). The ability to
retain information when power is lost makes this type of mem-
ory unique. Back-up batteries in the NVRAM device that keep
the memory active makes this possible.
A key feature of the RAM and ROM memory of the MFP module
is that it requires only one wait state. This means that the
microprocessor need only wait one clock cycle before it can
check the data in memory. This results in quicker operation.
I/O EXPANDER BUS
The I/O expander bus resides on the backplane of the module
mounting unit. This bus, an eight bit parallel bus, provides the
communication path for I/O data between control and I/O
modules. It supports up to 64 low power I/O modules. The bus
uses a protocol designed by Bailey Controls Company to ensure
data integrity. The bus bandwidth is 500 kilobytes per second,
however actual throughput is about 100 kilobytes per second.
I/O SECTION
The input and output section interface allows the microproces-
sor to read the switches that tell it how to operate and what
