AXIOMTEK DASP-52282, Руководство пользователя

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DASP-52282 Card User’s Manual
Theorem of Operation
30
3.3 Double Buffering Mechanism For Fast
Data Acquisition
To achieve gapless high speed data acquisition, a double
buffering mechanism has been designed and realized for
DASP-52282. The on board FIFO of DASP-52282 serves as the
hardware level data buffers, and a 256K WORD software level
data buffer is implemented by the ring 0 driver of DASP-52282.
3.3.1 On Board FIFO and FIFO Half Full Interrupt
The DASP-52282 provides a 1K WORD on board FIFO (first in
first out) buffer to support massive data transfer to its host. A FH
(half-full) interrupt supported by the on board FIFO is used to
launch batch data transfer mechanism of ring 0 driver of
DASP-52282. The following shows the functional block diagram
of massive data transfer of DASP-52282.
ADC
Analog Input
Digital Output
FIFO
IRQ Logic Chip Set
FIFO Half Full
IRQ n
Functional Block Diagram of Massive Data Transfer of
DASP-52282
When DASP-52282 is triggered to acquire data, the ADC
samples the analog input signal and pushes the converted AD
data to the on board FIFO. When free space of the on board
FIFO is less than its half capacity, a HF signal is fired and the
internal control logic of DASP-52282 produces an IRQ to the host.
The FIFO HF IRQ in the host is dispatched to the ring 0 driver of
DASP-52282, and a batch data transfer mechanism is launched
to transfer the acquired data in on board FIFO of DASP-52282 to
host, as show in following figure.