AXIOMTEK DASP-52282, Руководство пользователя

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DASP-52282 Card User’s Manual
Theorem of Operation
27
3.2.3 External Trigger Mode
To synchronize external event and data acquisition of the
DASP-52282, a series of external trigger mechanism, including
pre-trigger, middle trigger and post trigger, is provided. Based on
the hardware pacer design described in 3.2.2 and the gate
control logic for the hardware pacer clock, various external trigger
mode operations of DASP-52282 are realized. According to the
status of consumed external trigger signal and the amount of
acquired data counted by hardware logic circuit, the gate control
logic of AD conversion of DASP-52282 is emulates. With
pre-trigger mode operation, DASP-52282 acquires and keeps the
user specified amount of data before the external trigger signal
fired. With the post trigger operation, DASP-52282 acquires and
keeps the user specified amount of data after the external trigger
signal fired. The functional block diagram of external trigger
mode operation of DASP-52282 is depicted as below figure.
Principles of pre-trigger and post-trigger are also shown in
following.
ADC
Convert
Logic
Contrller
Tim er
Counter
Analog Input Digital Output
Convert Com m and
External Trigger
Functional Block Diagram of External Trigger of DASP-52282