DASP-52282 Card User’s Manual
Registry Structure and Format
44
4.2.8
DAC Channel 2 Output Latch Register
Write (Base A Offset 0x06-07)
D7
D6
D5
D4
D3
D2
D1
D0
DA Data to Channel 2 (D0-D11)
D15
D14
D13
D12
D11
D10
D9
D8
Reserved
DA Data to Channel 2
(D0-D11)
4.2.9
8254 Timer/Counter Register
Read/ Write (Base A Offset 0x08-0C)
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
8254 Counter 0, 1, and 2
Please refer to Intel’s “Micro-system Components Handbook” for
detailed.
4.2.10 8254 Timer/Counter Control Words
Register
Write (Base A Offset 0x0E)
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
8254 Control Words
Please refer to Intel’s “Micro-system Components Handbook” for
detailed.
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